| .. | .. |
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| 55 | 55 | .need_resume = mid_pci_need_resume, |
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| 56 | 56 | }; |
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| 57 | 57 | |
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| 58 | | -#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
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| 59 | | - |
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| 60 | 58 | /* |
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| 61 | 59 | * This table should be in sync with the one in |
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| 62 | 60 | * arch/x86/platform/intel-mid/pwr.c. |
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| 63 | 61 | */ |
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| 64 | 62 | static const struct x86_cpu_id lpss_cpu_ids[] = { |
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| 65 | | - ICPU(INTEL_FAM6_ATOM_SALTWELL_MID), |
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| 66 | | - ICPU(INTEL_FAM6_ATOM_SILVERMONT_MID), |
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| 63 | + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, NULL), |
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| 64 | + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL), |
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| 67 | 65 | {} |
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| 68 | 66 | }; |
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| 69 | 67 | |
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