write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/pci/ecam.c
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@@ -26,7 +26,7 @@
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  */
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 struct pci_config_window *pci_ecam_create(struct device *dev,
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 		struct resource *cfgres, struct resource *busr,
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-		struct pci_ecam_ops *ops)
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+		const struct pci_ecam_ops *ops)
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 {
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 	struct pci_config_window *cfg;
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 	unsigned int bus_range, bus_range_max, bsz;
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@@ -101,6 +101,7 @@
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 	pci_ecam_free(cfg);
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 	return ERR_PTR(err);
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 }
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+EXPORT_SYMBOL_GPL(pci_ecam_create);
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 void pci_ecam_free(struct pci_config_window *cfg)
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 {
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@@ -121,6 +122,7 @@
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 		release_resource(&cfg->res);
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 	kfree(cfg);
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 }
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+EXPORT_SYMBOL_GPL(pci_ecam_free);
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 /*
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  * Function to implement the pci_ops ->map_bus method
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@@ -143,9 +145,10 @@
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 		base = cfg->win + (busn << cfg->ops->bus_shift);
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 	return base + (devfn << devfn_shift) + where;
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 }
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+EXPORT_SYMBOL_GPL(pci_ecam_map_bus);
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 /* ECAM ops */
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-struct pci_ecam_ops pci_generic_ecam_ops = {
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+const struct pci_ecam_ops pci_generic_ecam_ops = {
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 	.bus_shift	= 20,
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 	.pci_ops	= {
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 		.map_bus	= pci_ecam_map_bus,
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@@ -153,10 +156,11 @@
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 		.write		= pci_generic_config_write,
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 	}
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 };
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+EXPORT_SYMBOL_GPL(pci_generic_ecam_ops);
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 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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 /* ECAM ops for 32-bit access only (non-compliant) */
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-struct pci_ecam_ops pci_32b_ops = {
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+const struct pci_ecam_ops pci_32b_ops = {
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 	.bus_shift	= 20,
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 	.pci_ops	= {
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 		.map_bus	= pci_ecam_map_bus,
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@@ -164,4 +168,14 @@
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 		.write		= pci_generic_config_write32,
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 	}
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 };
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+
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+/* ECAM ops for 32-bit read only (non-compliant) */
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+const struct pci_ecam_ops pci_32b_read_ops = {
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+	.bus_shift	= 20,
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+	.pci_ops	= {
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+		.map_bus	= pci_ecam_map_bus,
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+		.read		= pci_generic_config_read32,
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+		.write		= pci_generic_config_write,
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+	}
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+};
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 #endif