~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,14 +1,6 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 as
6		- * published by the Free Software Foundation.
7		- *
8		- * This program is distributed in the hope that it will be useful,
9		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*/
13	5
14	6	#ifndef __MT7530_H
..	..	@@ -18,6 +10,12 @@
18	10	#define MT7530_CPU_PORT 6
19	11	#define MT7530_NUM_FDB_RECORDS 2048
20	12	#define MT7530_ALL_MEMBERS 0xff
	13	+
	14	+enum mt753x_id {
	15	+ ID_MT7530 = 0,
	16	+ ID_MT7621 = 1,
	17	+ ID_MT7531 = 2,
	18	+};
21	19
22	20	#define NUM_TRGMII_CTRL 5
23	21
..	..	@@ -37,6 +35,39 @@
37	35	#define UNM_FFP_MASK UNM_FFP(~0)
38	36	#define UNU_FFP(x) (((x) & 0xff) << 8)
39	37	#define UNU_FFP_MASK UNU_FFP(~0)
	38	+#define CPU_EN BIT(7)
	39	+#define CPU_PORT(x) ((x) << 4)
	40	+#define CPU_MASK (0xf << 4)
	41	+#define MIRROR_EN BIT(3)
	42	+#define MIRROR_PORT(x) ((x) & 0x7)
	43	+#define MIRROR_MASK 0x7
	44	+
	45	+/* Registers for CPU forward control */
	46	+#define MT7531_CFC 0x4
	47	+#define MT7531_MIRROR_EN BIT(19)
	48	+#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
	49	+#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
	50	+#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
	51	+#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
	52	+
	53	+#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
	54	+ MT7531_CFC : MT7530_MFC)
	55	+#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
	56	+ MT7531_MIRROR_EN : MIRROR_EN)
	57	+#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
	58	+ MT7531_MIRROR_MASK : MIRROR_MASK)
	59	+
	60	+/* Registers for BPDU and PAE frame control*/
	61	+#define MT753X_BPC 0x24
	62	+#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
	63	+
	64	+enum mt753x_bpdu_port_fw {
	65	+ MT753X_BPDU_FOLLOW_MFC,
	66	+ MT753X_BPDU_CPU_EXCLUDE = 4,
	67	+ MT753X_BPDU_CPU_INCLUDE = 5,
	68	+ MT753X_BPDU_CPU_ONLY = 6,
	69	+ MT753X_BPDU_DROP = 7,
	70	+};
40	71
41	72	/* Registers for address table access */
42	73	#define MT7530_ATA1 0x74
..	..	@@ -142,6 +173,8 @@
142	173
143	174	/* Register for port control */
144	175	#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
	176	+#define PORT_TX_MIR BIT(9)
	177	+#define PORT_RX_MIR BIT(8)
145	178	#define PORT_VLAN(x) ((x) & 0x3)
146	179
147	180	enum mt7530_port_mode {
..	..	@@ -200,6 +233,7 @@
200	233	/* Register for port MAC control register */
201	234	#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
202	235	#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
	236	+#define PMCR_EXT_PHY BIT(17)
203	237	#define PMCR_MAC_MODE BIT(16)
204	238	#define PMCR_FORCE_MODE BIT(15)
205	239	#define PMCR_TX_EN BIT(14)
..	..	@@ -212,26 +246,48 @@
212	246	#define PMCR_FORCE_SPEED_100 BIT(2)
213	247	#define PMCR_FORCE_FDX BIT(1)
214	248	#define PMCR_FORCE_LNK BIT(0)
215		-#define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) \| PMCR_MAC_MODE \| \
	249	+#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 \| \
	250	+ PMCR_FORCE_SPEED_1000)
	251	+#define MT7531_FORCE_LNK BIT(31)
	252	+#define MT7531_FORCE_SPD BIT(30)
	253	+#define MT7531_FORCE_DPX BIT(29)
	254	+#define MT7531_FORCE_RX_FC BIT(28)
	255	+#define MT7531_FORCE_TX_FC BIT(27)
	256	+#define MT7531_FORCE_MODE (MT7531_FORCE_LNK \| \
	257	+ MT7531_FORCE_SPD \| \
	258	+ MT7531_FORCE_DPX \| \
	259	+ MT7531_FORCE_RX_FC \| \
	260	+ MT7531_FORCE_TX_FC)
	261	+#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
	262	+ MT7531_FORCE_MODE : \
	263	+ PMCR_FORCE_MODE)
	264	+#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN \| PMCR_FORCE_SPEED_1000 \| \
	265	+ PMCR_RX_EN \| PMCR_FORCE_SPEED_100 \| \
	266	+ PMCR_TX_FC_EN \| PMCR_RX_FC_EN \| \
	267	+ PMCR_FORCE_FDX \| PMCR_FORCE_LNK)
	268	+#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) \| \
	269	+ PMCR_IFG_XMIT(1) \| PMCR_MAC_MODE \| \
216	270	PMCR_BACKOFF_EN \| PMCR_BACKPR_EN \| \
217	271	PMCR_TX_EN \| PMCR_RX_EN \| \
218		- PMCR_TX_FC_EN \| PMCR_RX_FC_EN)
219		-#define PMCR_CPUP_LINK (PMCR_COMMON_LINK \| PMCR_FORCE_MODE \| \
	272	+ PMCR_TX_FC_EN \| PMCR_RX_FC_EN \| \
220	273	PMCR_FORCE_SPEED_1000 \| \
221		- PMCR_FORCE_FDX \| \
222		- PMCR_FORCE_LNK)
223		-#define PMCR_USERP_LINK PMCR_COMMON_LINK
224		-#define PMCR_FIXED_LINK (PMCR_IFG_XMIT(1) \| PMCR_MAC_MODE \| \
225		- PMCR_FORCE_MODE \| PMCR_TX_EN \| \
226		- PMCR_RX_EN \| PMCR_BACKPR_EN \| \
227		- PMCR_BACKOFF_EN \| \
228		- PMCR_FORCE_SPEED_1000 \| \
229		- PMCR_FORCE_FDX \| \
230		- PMCR_FORCE_LNK)
231		-#define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK \| \
232		- PMCR_TX_FC_EN \| PMCR_RX_FC_EN)
	274	+ PMCR_FORCE_FDX \| PMCR_FORCE_LNK)
233	275
234	276	#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
	277	+#define PMSR_EEE1G BIT(7)
	278	+#define PMSR_EEE100M BIT(6)
	279	+#define PMSR_RX_FC BIT(5)
	280	+#define PMSR_TX_FC BIT(4)
	281	+#define PMSR_SPEED_1000 BIT(3)
	282	+#define PMSR_SPEED_100 BIT(2)
	283	+#define PMSR_SPEED_10 0x00
	284	+#define PMSR_SPEED_MASK (PMSR_SPEED_100 \| PMSR_SPEED_1000)
	285	+#define PMSR_DPX BIT(1)
	286	+#define PMSR_LINK BIT(0)
	287	+
	288	+/* Register for port debug count */
	289	+#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
	290	+#define MT7531_DIS_CLR BIT(31)
235	291
236	292	/* Register for MIB */
237	293	#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
..	..	@@ -250,17 +306,138 @@
250	306	CCR_RX_OCT_CNT_BAD \| \
251	307	CCR_TX_OCT_CNT_GOOD \| \
252	308	CCR_TX_OCT_CNT_BAD)
	309	+
	310	+/* MT7531 SGMII register group */
	311	+#define MT7531_SGMII_REG_BASE 0x5000
	312	+#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
	313	+ ((p) - 5) * 0x1000 + (r))
	314	+
	315	+/* Register forSGMII PCS_CONTROL_1 */
	316	+#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
	317	+#define MT7531_SGMII_LINK_STATUS BIT(18)
	318	+#define MT7531_SGMII_AN_ENABLE BIT(12)
	319	+#define MT7531_SGMII_AN_RESTART BIT(9)
	320	+
	321	+/* Register for SGMII PCS_SPPED_ABILITY */
	322	+#define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
	323	+#define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
	324	+#define MT7531_SGMII_TX_CONFIG BIT(0)
	325	+
	326	+/* Register for SGMII_MODE */
	327	+#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
	328	+#define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
	329	+#define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
	330	+#define MT7531_SGMII_FORCE_DUPLEX BIT(4)
	331	+#define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
	332	+#define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
	333	+#define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
	334	+#define MT7531_SGMII_FORCE_SPEED_10 0
	335	+#define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
	336	+
	337	+enum mt7531_sgmii_force_duplex {
	338	+ MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
	339	+ MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
	340	+};
	341	+
	342	+/* Fields of QPHY_PWR_STATE_CTRL */
	343	+#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
	344	+#define MT7531_SGMII_PHYA_PWD BIT(4)
	345	+
	346	+/* Values of SGMII SPEED */
	347	+#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
	348	+#define MT7531_RG_TPHY_SPEED_MASK (BIT(2) \| BIT(3))
	349	+#define MT7531_RG_TPHY_SPEED_1_25G 0x0
	350	+#define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
	351	+
253	352	/* Register for system reset */
254	353	#define MT7530_SYS_CTRL 0x7000
255	354	#define SYS_CTRL_PHY_RST BIT(2)
256	355	#define SYS_CTRL_SW_RST BIT(1)
257	356	#define SYS_CTRL_REG_RST BIT(0)
258	357
	358	+/* Register for PHY Indirect Access Control */
	359	+#define MT7531_PHY_IAC 0x701C
	360	+#define MT7531_PHY_ACS_ST BIT(31)
	361	+#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
	362	+#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
	363	+#define MT7531_MDIO_CMD_MASK (0x3 << 18)
	364	+#define MT7531_MDIO_ST_MASK (0x3 << 16)
	365	+#define MT7531_MDIO_RW_DATA_MASK (0xffff)
	366	+#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
	367	+#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
	368	+#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
	369	+#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
	370	+#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
	371	+
	372	+enum mt7531_phy_iac_cmd {
	373	+ MT7531_MDIO_ADDR = 0,
	374	+ MT7531_MDIO_WRITE = 1,
	375	+ MT7531_MDIO_READ = 2,
	376	+ MT7531_MDIO_READ_CL45 = 3,
	377	+};
	378	+
	379	+/* MDIO_ST: MDIO start field */
	380	+enum mt7531_mdio_st {
	381	+ MT7531_MDIO_ST_CL45 = 0,
	382	+ MT7531_MDIO_ST_CL22 = 1,
	383	+};
	384	+
	385	+#define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) \| \
	386	+ MT7531_MDIO_CMD(MT7531_MDIO_READ))
	387	+#define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) \| \
	388	+ MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
	389	+#define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) \| \
	390	+ MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
	391	+#define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) \| \
	392	+ MT7531_MDIO_CMD(MT7531_MDIO_READ))
	393	+#define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) \| \
	394	+ MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
	395	+
	396	+/* Register for RGMII clock phase */
	397	+#define MT7531_CLKGEN_CTRL 0x7500
	398	+#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
	399	+#define CLK_SKEW_OUT_MASK GENMASK(9, 8)
	400	+#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
	401	+#define CLK_SKEW_IN_MASK GENMASK(7, 6)
	402	+#define RXCLK_NO_DELAY BIT(5)
	403	+#define TXCLK_NO_REVERSE BIT(4)
	404	+#define GP_MODE(x) (((x) & 0x3) << 1)
	405	+#define GP_MODE_MASK GENMASK(2, 1)
	406	+#define GP_CLK_EN BIT(0)
	407	+
	408	+enum mt7531_gp_mode {
	409	+ MT7531_GP_MODE_RGMII = 0,
	410	+ MT7531_GP_MODE_MII = 1,
	411	+ MT7531_GP_MODE_REV_MII = 2
	412	+};
	413	+
	414	+enum mt7531_clk_skew {
	415	+ MT7531_CLK_SKEW_NO_CHG = 0,
	416	+ MT7531_CLK_SKEW_DLY_100PPS = 1,
	417	+ MT7531_CLK_SKEW_DLY_200PPS = 2,
	418	+ MT7531_CLK_SKEW_REVERSE = 3,
	419	+};
	420	+
259	421	/* Register for hw trap status */
260	422	#define MT7530_HWTRAP 0x7800
	423	+#define HWTRAP_XTAL_MASK (BIT(10) \| BIT(9))
	424	+#define HWTRAP_XTAL_25MHZ (BIT(10) \| BIT(9))
	425	+#define HWTRAP_XTAL_40MHZ (BIT(10))
	426	+#define HWTRAP_XTAL_20MHZ (BIT(9))
	427	+
	428	+#define MT7531_HWTRAP 0x7800
	429	+#define HWTRAP_XTAL_FSEL_MASK BIT(7)
	430	+#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
	431	+#define HWTRAP_XTAL_FSEL_40MHZ 0
	432	+/* Unique fields of (M)HWSTRAP for MT7531 */
	433	+#define XTAL_FSEL_S 7
	434	+#define XTAL_FSEL_M BIT(7)
	435	+#define PHY_EN BIT(6)
	436	+#define CHG_STRAP BIT(8)
261	437
262	438	/* Register for hw trap modification */
263	439	#define MT7530_MHWTRAP 0x7804
	440	+#define MHWTRAP_PHY0_SEL BIT(20)
264	441	#define MHWTRAP_MANUAL BIT(16)
265	442	#define MHWTRAP_P5_MAC_SEL BIT(13)
266	443	#define MHWTRAP_P6_DIS BIT(8)
..	..	@@ -272,17 +449,39 @@
272	449	#define MT7530_TOP_SIG_CTRL 0x7808
273	450	#define TOP_SIG_CTRL_NORMAL (BIT(17) \| BIT(16))
274	451
	452	+#define MT7531_TOP_SIG_SR 0x780c
	453	+#define PAD_DUAL_SGMII_EN BIT(1)
	454	+#define PAD_MCM_SMI_EN BIT(0)
	455	+
275	456	#define MT7530_IO_DRV_CR 0x7810
276	457	#define P5_IO_CLK_DRV(x) ((x) & 0x3)
277	458	#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
	459	+
	460	+#define MT7531_CHIP_REV 0x781C
	461	+
	462	+#define MT7531_PLLGP_EN 0x7820
	463	+#define EN_COREPLL BIT(2)
	464	+#define SW_CLKSW BIT(1)
	465	+#define SW_PLLGP BIT(0)
278	466
279	467	#define MT7530_P6ECR 0x7830
280	468	#define P6_INTF_MODE_MASK 0x3
281	469	#define P6_INTF_MODE(x) ((x) & 0x3)
282	470
	471	+#define MT7531_PLLGP_CR0 0x78a8
	472	+#define RG_COREPLL_EN BIT(22)
	473	+#define RG_COREPLL_POSDIV_S 23
	474	+#define RG_COREPLL_POSDIV_M 0x3800000
	475	+#define RG_COREPLL_SDM_PCW_S 1
	476	+#define RG_COREPLL_SDM_PCW_M 0x3ffffe
	477	+#define RG_COREPLL_SDM_PCW_CHG BIT(0)
	478	+
	479	+/* Registers for RGMII and SGMII PLL clock */
	480	+#define MT7531_ANA_PLLGP_CR2 0x78b0
	481	+#define MT7531_ANA_PLLGP_CR5 0x78bc
	482	+
283	483	/* Registers for TRGMII on the both side */
284	484	#define MT7530_TRGMII_RCK_CTRL 0x7a00
285		-#define GSW_TRGMII_RCK_CTRL 0x300
286	485	#define RX_RST BIT(31)
287	486	#define RXC_DQSISEL BIT(30)
288	487	#define DQSI1_TAP_MASK (0x7f << 8)
..	..	@@ -291,30 +490,23 @@
291	490	#define DQSI0_TAP(x) ((x) & 0x7f)
292	491
293	492	#define MT7530_TRGMII_RCK_RTT 0x7a04
294		-#define GSW_TRGMII_RCK_RTT 0x304
295	493	#define DQS1_GATE BIT(31)
296	494	#define DQS0_GATE BIT(30)
297	495
298	496	#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
299		-#define GSW_TRGMII_RD(x) (0x310 + (x) * 8)
300	497	#define BSLIP_EN BIT(31)
301	498	#define EDGE_CHK BIT(30)
302	499	#define RD_TAP_MASK 0x7f
303	500	#define RD_TAP(x) ((x) & 0x7f)
304	501
305		-#define GSW_TRGMII_TXCTRL 0x340
306	502	#define MT7530_TRGMII_TXCTRL 0x7a40
307	503	#define TRAIN_TXEN BIT(31)
308	504	#define TXC_INV BIT(30)
309	505	#define TX_RST BIT(28)
310	506
311	507	#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
312		-#define GSW_TRGMII_TD_ODT(i) (0x354 + 8 * (i))
313	508	#define TD_DM_DRVP(x) ((x) & 0xf)
314	509	#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
315		-
316		-#define GSW_INTF_MODE 0x390
317		-#define INTF_MODE_TRGMII BIT(1)
318	510
319	511	#define MT7530_TRGMII_TCK_CTRL 0x7a78
320	512	#define TCK_TAP(x) (((x) & 0xf) << 8)
..	..	@@ -326,9 +518,24 @@
326	518	#define MT7530_P5RGMIITXCR 0x7b04
327	519	#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
328	520
	521	+/* Registers for GPIO mode */
	522	+#define MT7531_GPIO_MODE0 0x7c0c
	523	+#define MT7531_GPIO0_MASK GENMASK(3, 0)
	524	+#define MT7531_GPIO0_INTERRUPT 1
	525	+
	526	+#define MT7531_GPIO_MODE1 0x7c10
	527	+#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
	528	+#define MT7531_EXT_P_MDC_11 (2 << 12)
	529	+#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
	530	+#define MT7531_EXT_P_MDIO_12 (2 << 16)
	531	+
329	532	#define MT7530_CREV 0x7ffc
330	533	#define CHIP_NAME_SHIFT 16
331	534	#define MT7530_ID 0x7530
	535	+
	536	+#define MT7531_CREV 0x781C
	537	+#define CHIP_REV_M 0x0f
	538	+#define MT7531_ID 0x7531
332	539
333	540	/* Registers for core PLL access through mmd indirect */
334	541	#define CORE_PLL_GROUP2 0x401
..	..	@@ -346,6 +553,10 @@
346	553	#define RG_SYSPLL_DDSFBK_EN BIT(12)
347	554	#define RG_SYSPLL_BIAS_EN BIT(11)
348	555	#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
	556	+#define MT7531_PHY_PLL_OFF BIT(5)
	557	+#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
	558	+
	559	+#define MT753X_CTRL_PHY_ADDR 0
349	560
350	561	#define CORE_PLL_GROUP5 0x404
351	562	#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
..	..	@@ -416,7 +627,76 @@
416	627	bool enable;
417	628	u32 pm;
418	629	u16 pvid;
419		- bool vlan_filtering;
	630	+};
	631	+
	632	+/* Port 5 interface select definitions */
	633	+enum p5_interface_select {
	634	+ P5_DISABLED = 0,
	635	+ P5_INTF_SEL_PHY_P0,
	636	+ P5_INTF_SEL_PHY_P4,
	637	+ P5_INTF_SEL_GMAC5,
	638	+ P5_INTF_SEL_GMAC5_SGMII,
	639	+};
	640	+
	641	+static const char *p5_intf_modes(unsigned int p5_interface)
	642	+{
	643	+ switch (p5_interface) {
	644	+ case P5_DISABLED:
	645	+ return "DISABLED";
	646	+ case P5_INTF_SEL_PHY_P0:
	647	+ return "PHY P0";
	648	+ case P5_INTF_SEL_PHY_P4:
	649	+ return "PHY P4";
	650	+ case P5_INTF_SEL_GMAC5:
	651	+ return "GMAC5";
	652	+ case P5_INTF_SEL_GMAC5_SGMII:
	653	+ return "GMAC5_SGMII";
	654	+ default:
	655	+ return "unknown";
	656	+ }
	657	+}
	658	+
	659	+/* struct mt753x_info - This is the main data structure for holding the specific
	660	+ * part for each supported device
	661	+ * @sw_setup: Holding the handler to a device initialization
	662	+ * @phy_read: Holding the way reading PHY port
	663	+ * @phy_write: Holding the way writing PHY port
	664	+ * @pad_setup: Holding the way setting up the bus pad for a certain
	665	+ * MAC port
	666	+ * @phy_mode_supported: Check if the PHY type is being supported on a certain
	667	+ * port
	668	+ * @mac_port_validate: Holding the way to set addition validate type for a
	669	+ * certan MAC port
	670	+ * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain
	671	+ * MAC port
	672	+ * @mac_port_config: Holding the way setting up the PHY attribute to a
	673	+ * certain MAC port
	674	+ * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
	675	+ * certain MAC port
	676	+ * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
	677	+ * of the certain MAC port
	678	+ */
	679	+struct mt753x_info {
	680	+ enum mt753x_id id;
	681	+
	682	+ int (sw_setup)(struct dsa_switch ds);
	683	+ int (phy_read)(struct dsa_switch ds, int port, int regnum);
	684	+ int (phy_write)(struct dsa_switch ds, int port, int regnum, u16 val);
	685	+ int (pad_setup)(struct dsa_switch ds, phy_interface_t interface);
	686	+ int (cpu_port_config)(struct dsa_switch ds, int port);
	687	+ bool (phy_mode_supported)(struct dsa_switch ds, int port,
	688	+ const struct phylink_link_state *state);
	689	+ void (mac_port_validate)(struct dsa_switch ds, int port,
	690	+ unsigned long *supported);
	691	+ int (mac_port_get_state)(struct dsa_switch ds, int port,
	692	+ struct phylink_link_state *state);
	693	+ int (mac_port_config)(struct dsa_switch ds, int port,
	694	+ unsigned int mode,
	695	+ phy_interface_t interface);
	696	+ void (mac_pcs_an_restart)(struct dsa_switch ds, int port);
	697	+ void (mac_pcs_link_up)(struct dsa_switch ds, int port,
	698	+ unsigned int mode, phy_interface_t interface,
	699	+ int speed, int duplex);
420	700	};
421	701
422	702	/* struct mt7530_priv - This is the main data structure for holding the state
..	..	@@ -425,7 +705,6 @@
425	705	* @ds: The pointer to the dsa core structure
426	706	* @bus: The bus used for the device and built-in PHY
427	707	* @rstc: The pointer to reset control used by MCM
428		- * @ethernet: The regmap used for access TRGMII-based registers
429	708	* @core_pwr: The power supplied into the core
430	709	* @io_pwr: The power supplied into the I/O
431	710	* @reset: The descriptor for GPIO line tied to its reset pin
..	..	@@ -434,17 +713,25 @@
434	713	* @ports: Holding the state among ports
435	714	* @reg_mutex: The lock for protecting among process accessing
436	715	* registers
	716	+ * @p6_interface Holding the current port 6 interface
	717	+ * @p5_intf_sel: Holding the current port 5 interface select
437	718	*/
438	719	struct mt7530_priv {
439	720	struct device *dev;
440	721	struct dsa_switch *ds;
441	722	struct mii_bus *bus;
442	723	struct reset_control *rstc;
443		- struct regmap *ethernet;
444	724	struct regulator *core_pwr;
445	725	struct regulator *io_pwr;
446	726	struct gpio_desc *reset;
	727	+ const struct mt753x_info *info;
	728	+ unsigned int id;
447	729	bool mcm;
	730	+ phy_interface_t p6_interface;
	731	+ phy_interface_t p5_interface;
	732	+ unsigned int p5_intf_sel;
	733	+ u8 mirror_rx;
	734	+ u8 mirror_tx;
448	735
449	736	struct mt7530_port ports[MT7530_NUM_PORTS];
450	737	/* protect among processes for registers access*/