~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,32 +1,19 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Amlogic SD/eMMC driver for the GX/S905 family SoCs
3	4	*
4	5	* Copyright (c) 2016 BayLibre, SAS.
5	6	* Author: Kevin Hilman <khilman@baylibre.com>
6		- *
7		- * This program is free software; you can redistribute it and/or modify
8		- * it under the terms of version 2 of the GNU General Public License as
9		- * published by the Free Software Foundation.
10		- *
11		- * This program is distributed in the hope that it will be useful, but
12		- * WITHOUT ANY WARRANTY; without even the implied warranty of
13		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14		- * General Public License for more details.
15		- *
16		- * You should have received a copy of the GNU General Public License
17		- * along with this program; if not, see <http://www.gnu.org/licenses/>.
18		- * The full GNU General Public License is included in this distribution
19		- * in the file called COPYING.
20	7	*/
21	8	#include <linux/kernel.h>
22	9	#include <linux/module.h>
23	10	#include <linux/init.h>
24	11	#include <linux/delay.h>
25	12	#include <linux/device.h>
	13	+#include <linux/iopoll.h>
26	14	#include <linux/of_device.h>
27	15	#include <linux/platform_device.h>
28	16	#include <linux/ioport.h>
29		-#include <linux/spinlock.h>
30	17	#include <linux/dma-mapping.h>
31	18	#include <linux/mmc/host.h>
32	19	#include <linux/mmc/mmc.h>
..	..	@@ -49,6 +36,8 @@
49	36	#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
50	37	#define CLK_TX_PHASE_MASK GENMASK(11, 10)
51	38	#define CLK_RX_PHASE_MASK GENMASK(13, 12)
	39	+#define CLK_PHASE_0 0
	40	+#define CLK_PHASE_180 2
52	41	#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
53	42	#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
54	43	#define CLK_V2_ALWAYS_ON BIT(24)
..	..	@@ -57,16 +46,15 @@
57	46	#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
58	47	#define CLK_V3_ALWAYS_ON BIT(28)
59	48
60		-#define CLK_DELAY_STEP_PS 200
61		-#define CLK_PHASE_STEP 30
62		-#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
63		-
64	49	#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
65	50	#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
66	51	#define CLK_ALWAYS_ON(h) (h->data->always_on)
67	52
68	53	#define SD_EMMC_DELAY 0x4
69	54	#define SD_EMMC_ADJUST 0x8
	55	+#define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
	56	+#define ADJUST_DS_EN BIT(15)
	57	+#define ADJUST_ADJ_EN BIT(13)
70	58
71	59	#define SD_EMMC_DELAY1 0x4
72	60	#define SD_EMMC_DELAY2 0x8
..	..	@@ -128,6 +116,9 @@
128	116	#define SD_EMMC_TXD 0x94
129	117	#define SD_EMMC_LAST_REG SD_EMMC_TXD
130	118
	119	+#define SD_EMMC_SRAM_DATA_BUF_LEN 1536
	120	+#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
	121	+
131	122	#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
132	123	#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
133	124	#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
..	..	@@ -144,6 +135,7 @@
144	135	unsigned int tx_delay_mask;
145	136	unsigned int rx_delay_mask;
146	137	unsigned int always_on;
	138	+ unsigned int adjust;
147	139	};
148	140
149	141	struct sd_emmc_desc {
..	..	@@ -159,20 +151,21 @@
159	151	struct mmc_host *mmc;
160	152	struct mmc_command *cmd;
161	153
162		- spinlock_t lock;
163	154	void __iomem *regs;
164	155	struct clk *core_clk;
	156	+ struct clk *mux_clk;
165	157	struct clk *mmc_clk;
166		- struct clk *rx_clk;
167		- struct clk *tx_clk;
168	158	unsigned long req_rate;
	159	+ bool ddr;
	160	+
	161	+ bool dram_access_quirk;
169	162
170	163	struct pinctrl *pinctrl;
171		- struct pinctrl_state *pins_default;
172	164	struct pinctrl_state *pins_clk_gate;
173	165
174	166	unsigned int bounce_buf_size;
175	167	void *bounce_buf;
	168	+ void __iomem *bounce_iomem_buf;
176	169	dma_addr_t bounce_dma_addr;
177	170	struct sd_emmc_desc *descs;
178	171	dma_addr_t descs_dma_addr;
..	..	@@ -180,6 +173,8 @@
180	173	int irq;
181	174
182	175	bool vqmmc_enabled;
	176	+ bool needs_pre_post_req;
	177	+
183	178	};
184	179
185	180	#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
..	..	@@ -204,90 +199,6 @@
204	199	#define CMD_DATA_SRAM BIT(0)
205	200	#define CMD_RESP_MASK GENMASK(31, 1)
206	201	#define CMD_RESP_SRAM BIT(0)
207		-
208		-struct meson_mmc_phase {
209		- struct clk_hw hw;
210		- void __iomem *reg;
211		- unsigned long phase_mask;
212		- unsigned long delay_mask;
213		- unsigned int delay_step_ps;
214		-};
215		-
216		-#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
217		-
218		-static int meson_mmc_clk_get_phase(struct clk_hw *hw)
219		-{
220		- struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
221		- unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
222		- unsigned long period_ps, p, d;
223		- int degrees;
224		- u32 val;
225		-
226		- val = readl(mmc->reg);
227		- p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
228		- degrees = p * 360 / phase_num;
229		-
230		- if (mmc->delay_mask) {
231		- period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
232		- clk_get_rate(hw->clk));
233		- d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
234		- degrees += d * mmc->delay_step_ps * 360 / period_ps;
235		- degrees %= 360;
236		- }
237		-
238		- return degrees;
239		-}
240		-
241		-static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
242		- unsigned int phase,
243		- unsigned int delay)
244		-{
245		- u32 val;
246		-
247		- val = readl(mmc->reg);
248		- val &= ~mmc->phase_mask;
249		- val \|= phase << __ffs(mmc->phase_mask);
250		-
251		- if (mmc->delay_mask) {
252		- val &= ~mmc->delay_mask;
253		- val \|= delay << __ffs(mmc->delay_mask);
254		- }
255		-
256		- writel(val, mmc->reg);
257		-}
258		-
259		-static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
260		-{
261		- struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
262		- unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
263		- unsigned long period_ps, d = 0, r;
264		- uint64_t p;
265		-
266		- p = degrees % 360;
267		-
268		- if (!mmc->delay_mask) {
269		- p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
270		- } else {
271		- period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
272		- clk_get_rate(hw->clk));
273		-
274		- /* First compute the phase index (p), the remainder (r) is the
275		- * part we'll try to acheive using the delays (d).
276		- */
277		- r = do_div(p, 360 / phase_num);
278		- d = DIV_ROUND_CLOSEST(r * period_ps,
279		- 360 * mmc->delay_step_ps);
280		- d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
281		- }
282		-
283		- meson_mmc_apply_phase_delay(mmc, p, d);
284		- return 0;
285		-}
286		-
287		-static const struct clk_ops meson_mmc_clk_phase_ops = {
288		- .get_phase = meson_mmc_clk_get_phase,
289		- .set_phase = meson_mmc_clk_set_phase,
290		-};
291	202
292	203	static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
293	204	{
..	..	@@ -315,10 +226,19 @@
315	226	static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
316	227	struct mmc_request *mrq)
317	228	{
	229	+ struct meson_host *host = mmc_priv(mmc);
318	230	struct mmc_data *data = mrq->data;
319	231	struct scatterlist *sg;
320	232	int i;
321	233	bool use_desc_chain_mode = true;
	234	+
	235	+ /*
	236	+ * When Controller DMA cannot directly access DDR memory, disable
	237	+ * support for Chain Mode to directly use the internal SRAM using
	238	+ * the bounce buffer mode.
	239	+ */
	240	+ if (host->dram_access_quirk)
	241	+ return;
322	242
323	243	/*
324	244	* Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
..	..	@@ -381,16 +301,6 @@
381	301	mmc_get_dma_dir(data));
382	302	}
383	303
384		-static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
385		-{
386		- if (ios->timing == MMC_TIMING_MMC_DDR52 \|\|
387		- ios->timing == MMC_TIMING_UHS_DDR50 \|\|
388		- ios->timing == MMC_TIMING_MMC_HS400)
389		- return true;
390		-
391		- return false;
392		-}
393		-
394	304	/*
395	305	* Gating the clock on this controller is tricky. It seems the mmc clock
396	306	* is also used by the controller. It may crash during some operation if the
..	..	@@ -419,7 +329,7 @@
419	329	u32 cfg;
420	330
421	331	if (host->pins_clk_gate)
422		- pinctrl_select_state(host->pinctrl, host->pins_default);
	332	+ pinctrl_select_default_state(host->dev);
423	333
424	334	/* Make sure the clock is not stopped in the controller */
425	335	cfg = readl(host->regs + SD_EMMC_CFG);
..	..	@@ -427,35 +337,40 @@
427	337	writel(cfg, host->regs + SD_EMMC_CFG);
428	338	}
429	339
430		-static int meson_mmc_clk_set(struct meson_host host, struct mmc_ios ios)
	340	+static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
	341	+ bool ddr)
431	342	{
432	343	struct mmc_host *mmc = host->mmc;
433		- unsigned long rate = ios->clock;
434	344	int ret;
435	345	u32 cfg;
436	346
437		- /* DDR modes require higher module clock */
438		- if (meson_mmc_timing_is_ddr(ios))
439		- rate <<= 1;
440		-
441	347	/* Same request - bail-out */
442		- if (host->req_rate == rate)
	348	+ if (host->ddr == ddr && host->req_rate == rate)
443	349	return 0;
444	350
445	351	/* stop clock */
446	352	meson_mmc_clk_gate(host);
447	353	host->req_rate = 0;
	354	+ mmc->actual_clock = 0;
448	355
449		- if (!rate) {
450		- mmc->actual_clock = 0;
451		- /* return with clock being stopped */
	356	+ /* return with clock being stopped */
	357	+ if (!rate)
452	358	return 0;
453		- }
454	359
455	360	/* Stop the clock during rate change to avoid glitches */
456	361	cfg = readl(host->regs + SD_EMMC_CFG);
457	362	cfg \|= CFG_STOP_CLOCK;
458	363	writel(cfg, host->regs + SD_EMMC_CFG);
	364	+
	365	+ if (ddr) {
	366	+ /* DDR modes require higher module clock */
	367	+ rate <<= 1;
	368	+ cfg \|= CFG_DDR;
	369	+ } else {
	370	+ cfg &= ~CFG_DDR;
	371	+ }
	372	+ writel(cfg, host->regs + SD_EMMC_CFG);
	373	+ host->ddr = ddr;
459	374
460	375	ret = clk_set_rate(host->mmc_clk, rate);
461	376	if (ret) {
..	..	@@ -468,12 +383,14 @@
468	383	mmc->actual_clock = clk_get_rate(host->mmc_clk);
469	384
470	385	/* We should report the real output frequency of the controller */
471		- if (meson_mmc_timing_is_ddr(ios))
	386	+ if (ddr) {
	387	+ host->req_rate >>= 1;
472	388	mmc->actual_clock >>= 1;
	389	+ }
473	390
474	391	dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
475		- if (ios->clock != mmc->actual_clock)
476		- dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
	392	+ if (rate != mmc->actual_clock)
	393	+ dev_dbg(host->dev, "requested rate was %lu\n", rate);
477	394
478	395	/* (re)start clock */
479	396	meson_mmc_clk_ungate(host);
..	..	@@ -491,8 +408,6 @@
491	408	struct clk_init_data init;
492	409	struct clk_mux *mux;
493	410	struct clk_divider *div;
494		- struct meson_mmc_phase core, tx, *rx;
495		- struct clk *clk;
496	411	char clk_name[32];
497	412	int i, ret = 0;
498	413	const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
..	..	@@ -500,9 +415,11 @@
500	415	u32 clk_reg;
501	416
502	417	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
503		- clk_reg = 0;
504		- clk_reg \|= CLK_ALWAYS_ON(host);
	418	+ clk_reg = CLK_ALWAYS_ON(host);
505	419	clk_reg \|= CLK_DIV_MASK;
	420	+ clk_reg \|= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
	421	+ clk_reg \|= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
	422	+ clk_reg \|= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
506	423	writel(clk_reg, host->regs + SD_EMMC_CLOCK);
507	424
508	425	/* get the mux parents */
..	..	@@ -512,11 +429,9 @@
512	429
513	430	snprintf(name, sizeof(name), "clkin%d", i);
514	431	clk = devm_clk_get(host->dev, name);
515		- if (IS_ERR(clk)) {
516		- if (clk != ERR_PTR(-EPROBE_DEFER))
517		- dev_err(host->dev, "Missing clock %s\n", name);
518		- return PTR_ERR(clk);
519		- }
	432	+ if (IS_ERR(clk))
	433	+ return dev_err_probe(host->dev, PTR_ERR(clk),
	434	+ "Missing clock %s\n", name);
520	435
521	436	mux_parent_names[i] = __clk_get_name(clk);
522	437	}
..	..	@@ -538,9 +453,9 @@
538	453	mux->mask = CLK_SRC_MASK >> mux->shift;
539	454	mux->hw.init = &init;
540	455
541		- clk = devm_clk_register(host->dev, &mux->hw);
542		- if (WARN_ON(IS_ERR(clk)))
543		- return PTR_ERR(clk);
	456	+ host->mux_clk = devm_clk_register(host->dev, &mux->hw);
	457	+ if (WARN_ON(IS_ERR(host->mux_clk)))
	458	+ return PTR_ERR(host->mux_clk);
544	459
545	460	/* create the divider */
546	461	div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
..	..	@@ -551,7 +466,7 @@
551	466	init.name = clk_name;
552	467	init.ops = &clk_divider_ops;
553	468	init.flags = CLK_SET_RATE_PARENT;
554		- clk_parent[0] = __clk_get_name(clk);
	469	+ clk_parent[0] = __clk_get_name(host->mux_clk);
555	470	init.parent_names = clk_parent;
556	471	init.num_parents = 1;
557	472
..	..	@@ -561,76 +476,9 @@
561	476	div->hw.init = &init;
562	477	div->flags = CLK_DIVIDER_ONE_BASED;
563	478
564		- clk = devm_clk_register(host->dev, &div->hw);
565		- if (WARN_ON(IS_ERR(clk)))
566		- return PTR_ERR(clk);
567		-
568		- /* create the mmc core clock */
569		- core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
570		- if (!core)
571		- return -ENOMEM;
572		-
573		- snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
574		- init.name = clk_name;
575		- init.ops = &meson_mmc_clk_phase_ops;
576		- init.flags = CLK_SET_RATE_PARENT;
577		- clk_parent[0] = __clk_get_name(clk);
578		- init.parent_names = clk_parent;
579		- init.num_parents = 1;
580		-
581		- core->reg = host->regs + SD_EMMC_CLOCK;
582		- core->phase_mask = CLK_CORE_PHASE_MASK;
583		- core->hw.init = &init;
584		-
585		- host->mmc_clk = devm_clk_register(host->dev, &core->hw);
586		- if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
	479	+ host->mmc_clk = devm_clk_register(host->dev, &div->hw);
	480	+ if (WARN_ON(IS_ERR(host->mmc_clk)))
587	481	return PTR_ERR(host->mmc_clk);
588		-
589		- /* create the mmc tx clock */
590		- tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
591		- if (!tx)
592		- return -ENOMEM;
593		-
594		- snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
595		- init.name = clk_name;
596		- init.ops = &meson_mmc_clk_phase_ops;
597		- init.flags = 0;
598		- clk_parent[0] = __clk_get_name(host->mmc_clk);
599		- init.parent_names = clk_parent;
600		- init.num_parents = 1;
601		-
602		- tx->reg = host->regs + SD_EMMC_CLOCK;
603		- tx->phase_mask = CLK_TX_PHASE_MASK;
604		- tx->delay_mask = CLK_TX_DELAY_MASK(host);
605		- tx->delay_step_ps = CLK_DELAY_STEP_PS;
606		- tx->hw.init = &init;
607		-
608		- host->tx_clk = devm_clk_register(host->dev, &tx->hw);
609		- if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
610		- return PTR_ERR(host->tx_clk);
611		-
612		- /* create the mmc rx clock */
613		- rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
614		- if (!rx)
615		- return -ENOMEM;
616		-
617		- snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
618		- init.name = clk_name;
619		- init.ops = &meson_mmc_clk_phase_ops;
620		- init.flags = 0;
621		- clk_parent[0] = __clk_get_name(host->mmc_clk);
622		- init.parent_names = clk_parent;
623		- init.num_parents = 1;
624		-
625		- rx->reg = host->regs + SD_EMMC_CLOCK;
626		- rx->phase_mask = CLK_RX_PHASE_MASK;
627		- rx->delay_mask = CLK_RX_DELAY_MASK(host);
628		- rx->delay_step_ps = CLK_DELAY_STEP_PS;
629		- rx->hw.init = &init;
630		-
631		- host->rx_clk = devm_clk_register(host->dev, &rx->hw);
632		- if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
633		- return PTR_ERR(host->rx_clk);
634	482
635	483	/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
636	484	host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
..	..	@@ -638,114 +486,94 @@
638	486	if (ret)
639	487	return ret;
640	488
641		- /*
642		- * Set phases : These values are mostly the datasheet recommended ones
643		- * except for the Tx phase. Datasheet recommends 180 but some cards
644		- * fail at initialisation with it. 270 works just fine, it fixes these
645		- * initialisation issues and enable eMMC DDR52 mode.
646		- */
647		- clk_set_phase(host->mmc_clk, 180);
648		- clk_set_phase(host->tx_clk, 270);
649		- clk_set_phase(host->rx_clk, 0);
650		-
651	489	return clk_prepare_enable(host->mmc_clk);
652	490	}
653	491
654		-static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
	492	+static void meson_mmc_disable_resampling(struct meson_host *host)
655	493	{
656		- DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
657		- DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
	494	+ unsigned int val = readl(host->regs + host->data->adjust);
658	495
659		- /*
660		- * shift the bitmap right and reintroduce the dropped bits on the left
661		- * of the bitmap
662		- */
663		- bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
664		- bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
665		- CLK_PHASE_POINT_NUM);
666		- bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
	496	+ val &= ~ADJUST_ADJ_EN;
	497	+ writel(val, host->regs + host->data->adjust);
667	498	}
668	499
669		-static void meson_mmc_find_next_region(unsigned long *map,
670		- unsigned long *start,
671		- unsigned long *stop)
	500	+static void meson_mmc_reset_resampling(struct meson_host *host)
672	501	{
673		- start = find_next_bit(map, CLK_PHASE_POINT_NUM, start);
674		- stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, start);
	502	+ unsigned int val;
	503	+
	504	+ meson_mmc_disable_resampling(host);
	505	+
	506	+ val = readl(host->regs + host->data->adjust);
	507	+ val &= ~ADJUST_ADJ_DELAY_MASK;
	508	+ writel(val, host->regs + host->data->adjust);
675	509	}
676	510
677		-static int meson_mmc_find_tuning_point(unsigned long *test)
678		-{
679		- unsigned long shift, stop, offset = 0, start = 0, size = 0;
680		-
681		- /* Get the all good/all bad situation out the way */
682		- if (bitmap_full(test, CLK_PHASE_POINT_NUM))
683		- return 0; /* All points are good so point 0 will do */
684		- else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
685		- return -EIO; /* No successful tuning point */
686		-
687		- /*
688		- * Now we know there is a least one region find. Make sure it does
689		- * not wrap by the shifting the bitmap if necessary
690		- */
691		- shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
692		- if (shift != 0)
693		- meson_mmc_shift_map(test, shift);
694		-
695		- while (start < CLK_PHASE_POINT_NUM) {
696		- meson_mmc_find_next_region(test, &start, &stop);
697		-
698		- if ((stop - start) > size) {
699		- offset = start;
700		- size = stop - start;
701		- }
702		-
703		- start = stop;
704		- }
705		-
706		- /* Get the center point of the region */
707		- offset += (size / 2);
708		-
709		- /* Shift the result back */
710		- offset = (offset + shift) % CLK_PHASE_POINT_NUM;
711		-
712		- return offset;
713		-}
714		-
715		-static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
716		- struct clk *clk)
717		-{
718		- int point, ret;
719		- DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
720		-
721		- dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
722		- __clk_get_name(clk));
723		- bitmap_zero(test, CLK_PHASE_POINT_NUM);
724		-
725		- /* Explore tuning points */
726		- for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
727		- clk_set_phase(clk, point * CLK_PHASE_STEP);
728		- ret = mmc_send_tuning(mmc, opcode, NULL);
729		- if (!ret)
730		- set_bit(point, test);
731		- }
732		-
733		- /* Find the optimal tuning point and apply it */
734		- point = meson_mmc_find_tuning_point(test);
735		- if (point < 0)
736		- return point; /* tuning failed */
737		-
738		- clk_set_phase(clk, point * CLK_PHASE_STEP);
739		- dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
740		- clk_get_phase(clk));
741		- return 0;
742		-}
743		-
744		-static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
	511	+static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
745	512	{
746	513	struct meson_host *host = mmc_priv(mmc);
	514	+ unsigned int val, dly, max_dly, i;
	515	+ int ret;
747	516
748		- return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
	517	+ /* Resampling is done using the source clock */
	518	+ max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
	519	+ clk_get_rate(host->mmc_clk));
	520	+
	521	+ val = readl(host->regs + host->data->adjust);
	522	+ val \|= ADJUST_ADJ_EN;
	523	+ writel(val, host->regs + host->data->adjust);
	524	+
	525	+ if (mmc_doing_retune(mmc))
	526	+ dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
	527	+ else
	528	+ dly = 0;
	529	+
	530	+ for (i = 0; i < max_dly; i++) {
	531	+ val &= ~ADJUST_ADJ_DELAY_MASK;
	532	+ val \|= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
	533	+ writel(val, host->regs + host->data->adjust);
	534	+
	535	+ ret = mmc_send_tuning(mmc, opcode, NULL);
	536	+ if (!ret) {
	537	+ dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
	538	+ (dly + i) % max_dly);
	539	+ return 0;
	540	+ }
	541	+ }
	542	+
	543	+ meson_mmc_reset_resampling(host);
	544	+ return -EIO;
	545	+}
	546	+
	547	+static int meson_mmc_prepare_ios_clock(struct meson_host *host,
	548	+ struct mmc_ios *ios)
	549	+{
	550	+ bool ddr;
	551	+
	552	+ switch (ios->timing) {
	553	+ case MMC_TIMING_MMC_DDR52:
	554	+ case MMC_TIMING_UHS_DDR50:
	555	+ ddr = true;
	556	+ break;
	557	+
	558	+ default:
	559	+ ddr = false;
	560	+ break;
	561	+ }
	562	+
	563	+ return meson_mmc_clk_set(host, ios->clock, ddr);
	564	+}
	565	+
	566	+static void meson_mmc_check_resampling(struct meson_host *host,
	567	+ struct mmc_ios *ios)
	568	+{
	569	+ switch (ios->timing) {
	570	+ case MMC_TIMING_LEGACY:
	571	+ case MMC_TIMING_MMC_HS:
	572	+ case MMC_TIMING_SD_HS:
	573	+ case MMC_TIMING_MMC_DDR52:
	574	+ meson_mmc_disable_resampling(host);
	575	+ break;
	576	+ }
749	577	}
750	578
751	579	static void meson_mmc_set_ios(struct mmc_host mmc, struct mmc_ios ios)
..	..	@@ -773,9 +601,6 @@
773	601	case MMC_POWER_UP:
774	602	if (!IS_ERR(mmc->supply.vmmc))
775	603	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
776		-
777		- /* Reset rx phase */
778		- clk_set_phase(host->rx_clk, 0);
779	604
780	605	break;
781	606
..	..	@@ -813,20 +638,13 @@
813	638	val = readl(host->regs + SD_EMMC_CFG);
814	639	val &= ~CFG_BUS_WIDTH_MASK;
815	640	val \|= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
	641	+ writel(val, host->regs + SD_EMMC_CFG);
816	642
817		- val &= ~CFG_DDR;
818		- if (meson_mmc_timing_is_ddr(ios))
819		- val \|= CFG_DDR;
820		-
821		- val &= ~CFG_CHK_DS;
822		- if (ios->timing == MMC_TIMING_MMC_HS400)
823		- val \|= CFG_CHK_DS;
824		-
825		- err = meson_mmc_clk_set(host, ios);
	643	+ meson_mmc_check_resampling(host, ios);
	644	+ err = meson_mmc_prepare_ios_clock(host, ios);
826	645	if (err)
827	646	dev_err(host->dev, "Failed to set clock: %d\n,", err);
828	647
829		- writel(val, host->regs + SD_EMMC_CFG);
830	648	dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
831	649	}
832	650
..	..	@@ -836,6 +654,8 @@
836	654	struct meson_host *host = mmc_priv(mmc);
837	655
838	656	host->cmd = NULL;
	657	+ if (host->needs_pre_post_req)
	658	+ meson_mmc_post_req(mmc, mrq, 0);
839	659	mmc_request_done(host->mmc, mrq);
840	660	}
841	661
..	..	@@ -919,6 +739,53 @@
919	739	writel(start, host->regs + SD_EMMC_START);
920	740	}
921	741
	742	+/* local sg copy for dram_access_quirk */
	743	+static void meson_mmc_copy_buffer(struct meson_host host, struct mmc_data data,
	744	+ size_t buflen, bool to_buffer)
	745	+{
	746	+ unsigned int sg_flags = SG_MITER_ATOMIC;
	747	+ struct scatterlist *sgl = data->sg;
	748	+ unsigned int nents = data->sg_len;
	749	+ struct sg_mapping_iter miter;
	750	+ unsigned int offset = 0;
	751	+
	752	+ if (to_buffer)
	753	+ sg_flags \|= SG_MITER_FROM_SG;
	754	+ else
	755	+ sg_flags \|= SG_MITER_TO_SG;
	756	+
	757	+ sg_miter_start(&miter, sgl, nents, sg_flags);
	758	+
	759	+ while ((offset < buflen) && sg_miter_next(&miter)) {
	760	+ unsigned int buf_offset = 0;
	761	+ unsigned int len, left;
	762	+ u32 *buf = miter.addr;
	763	+
	764	+ len = min(miter.length, buflen - offset);
	765	+ left = len;
	766	+
	767	+ if (to_buffer) {
	768	+ do {
	769	+ writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
	770	+
	771	+ buf_offset += 4;
	772	+ left -= 4;
	773	+ } while (left);
	774	+ } else {
	775	+ do {
	776	+ *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
	777	+
	778	+ buf_offset += 4;
	779	+ left -= 4;
	780	+ } while (left);
	781	+ }
	782	+
	783	+ offset += len;
	784	+ }
	785	+
	786	+ sg_miter_stop(&miter);
	787	+}
	788	+
922	789	static void meson_mmc_start_cmd(struct mmc_host mmc, struct mmc_command cmd)
923	790	{
924	791	struct meson_host *host = mmc_priv(mmc);
..	..	@@ -962,8 +829,11 @@
962	829	if (data->flags & MMC_DATA_WRITE) {
963	830	cmd_cfg \|= CMD_CFG_DATA_WR;
964	831	WARN_ON(xfer_bytes > host->bounce_buf_size);
965		- sg_copy_to_buffer(data->sg, data->sg_len,
966		- host->bounce_buf, xfer_bytes);
	832	+ if (host->dram_access_quirk)
	833	+ meson_mmc_copy_buffer(host, data, xfer_bytes, true);
	834	+ else
	835	+ sg_copy_to_buffer(data->sg, data->sg_len,
	836	+ host->bounce_buf, xfer_bytes);
967	837	dma_wmb();
968	838	}
969	839
..	..	@@ -982,28 +852,56 @@
982	852	writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
983	853	}
984	854
	855	+static int meson_mmc_validate_dram_access(struct mmc_host mmc, struct mmc_data data)
	856	+{
	857	+ struct scatterlist *sg;
	858	+ int i;
	859	+
	860	+ /* Reject request if any element offset or size is not 32bit aligned */
	861	+ for_each_sg(data->sg, sg, data->sg_len, i) {
	862	+ if (!IS_ALIGNED(sg->offset, sizeof(u32)) \|\|
	863	+ !IS_ALIGNED(sg->length, sizeof(u32))) {
	864	+ dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
	865	+ data->sg->offset, data->sg->length);
	866	+ return -EINVAL;
	867	+ }
	868	+ }
	869	+
	870	+ return 0;
	871	+}
	872	+
985	873	static void meson_mmc_request(struct mmc_host mmc, struct mmc_request mrq)
986	874	{
987	875	struct meson_host *host = mmc_priv(mmc);
988		- bool needs_pre_post_req = mrq->data &&
	876	+ host->needs_pre_post_req = mrq->data &&
989	877	!(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
990	878
991		- if (needs_pre_post_req) {
992		- meson_mmc_get_transfer_mode(mmc, mrq);
993		- if (!meson_mmc_desc_chain_mode(mrq->data))
994		- needs_pre_post_req = false;
	879	+ /*
	880	+ * The memory at the end of the controller used as bounce buffer for
	881	+ * the dram_access_quirk only accepts 32bit read/write access,
	882	+ * check the aligment and length of the data before starting the request.
	883	+ */
	884	+ if (host->dram_access_quirk && mrq->data) {
	885	+ mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
	886	+ if (mrq->cmd->error) {
	887	+ mmc_request_done(mmc, mrq);
	888	+ return;
	889	+ }
995	890	}
996	891
997		- if (needs_pre_post_req)
	892	+ if (host->needs_pre_post_req) {
	893	+ meson_mmc_get_transfer_mode(mmc, mrq);
	894	+ if (!meson_mmc_desc_chain_mode(mrq->data))
	895	+ host->needs_pre_post_req = false;
	896	+ }
	897	+
	898	+ if (host->needs_pre_post_req)
998	899	meson_mmc_pre_req(mmc, mrq);
999	900
1000	901	/* Stop execution */
1001	902	writel(0, host->regs + SD_EMMC_START);
1002	903
1003	904	meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
1004		-
1005		- if (needs_pre_post_req)
1006		- meson_mmc_post_req(mmc, mrq, 0);
1007	905	}
1008	906
1009	907	static void meson_mmc_read_resp(struct mmc_host mmc, struct mmc_command cmd)
..	..	@@ -1042,7 +940,8 @@
1042	940	if (WARN_ON(!host) \|\| WARN_ON(!host->cmd))
1043	941	return IRQ_NONE;
1044	942
1045		- spin_lock(&host->lock);
	943	+ /* ack all raised interrupts */
	944	+ writel(status, host->regs + SD_EMMC_STATUS);
1046	945
1047	946	cmd = host->cmd;
1048	947	data = cmd->data;
..	..	@@ -1071,17 +970,11 @@
1071	970	if (status & (IRQ_END_OF_CHAIN \| IRQ_RESP_STATUS)) {
1072	971	if (data && !cmd->error)
1073	972	data->bytes_xfered = data->blksz * data->blocks;
1074		- if (meson_mmc_bounce_buf_read(data) \|\|
1075		- meson_mmc_get_next_command(cmd))
1076		- ret = IRQ_WAKE_THREAD;
1077		- else
1078		- ret = IRQ_HANDLED;
	973	+
	974	+ return IRQ_WAKE_THREAD;
1079	975	}
1080	976
1081	977	out:
1082		- /* ack all enabled interrupts */
1083		- writel(irq_en, host->regs + SD_EMMC_STATUS);
1084		-
1085	978	if (cmd->error) {
1086	979	/* Stop desc in case of errors */
1087	980	u32 start = readl(host->regs + SD_EMMC_START);
..	..	@@ -1090,16 +983,11 @@
1090	983	writel(start, host->regs + SD_EMMC_START);
1091	984	}
1092	985
1093		- if (ret == IRQ_HANDLED)
1094		- meson_mmc_request_done(host->mmc, cmd->mrq);
1095		-
1096		- spin_unlock(&host->lock);
1097	986	return ret;
1098	987	}
1099	988
1100	989	static int meson_mmc_wait_desc_stop(struct meson_host *host)
1101	990	{
1102		- int loop;
1103	991	u32 status;
1104	992
1105	993	/*
..	..	@@ -1109,20 +997,10 @@
1109	997	* If we don't confirm the descriptor is stopped, it might raise new
1110	998	* IRQs after we have called mmc_request_done() which is bad.
1111	999	*/
1112		- for (loop = 50; loop; loop--) {
1113		- status = readl(host->regs + SD_EMMC_STATUS);
1114		- if (status & (STATUS_BUSY \| STATUS_DESC_BUSY))
1115		- udelay(100);
1116		- else
1117		- break;
1118		- }
1119	1000
1120		- if (status & (STATUS_BUSY \| STATUS_DESC_BUSY)) {
1121		- dev_err(host->dev, "Timed out waiting for host to stop\n");
1122		- return -ETIMEDOUT;
1123		- }
1124		-
1125		- return 0;
	1001	+ return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
	1002	+ !(status & (STATUS_BUSY \| STATUS_DESC_BUSY)),
	1003	+ 100, 5000);
1126	1004	}
1127	1005
1128	1006	static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
..	..	@@ -1146,8 +1024,11 @@
1146	1024	if (meson_mmc_bounce_buf_read(data)) {
1147	1025	xfer_bytes = data->blksz * data->blocks;
1148	1026	WARN_ON(xfer_bytes > host->bounce_buf_size);
1149		- sg_copy_from_buffer(data->sg, data->sg_len,
1150		- host->bounce_buf, xfer_bytes);
	1027	+ if (host->dram_access_quirk)
	1028	+ meson_mmc_copy_buffer(host, data, xfer_bytes, false);
	1029	+ else
	1030	+ sg_copy_from_buffer(data->sg, data->sg_len,
	1031	+ host->bounce_buf, xfer_bytes);
1151	1032	}
1152	1033
1153	1034	next_cmd = meson_mmc_get_next_command(cmd);
..	..	@@ -1201,6 +1082,8 @@
1201	1082
1202	1083	static int meson_mmc_voltage_switch(struct mmc_host mmc, struct mmc_ios ios)
1203	1084	{
	1085	+ int ret;
	1086	+
1204	1087	/* vqmmc regulator is available */
1205	1088	if (!IS_ERR(mmc->supply.vqmmc)) {
1206	1089	/*
..	..	@@ -1210,7 +1093,8 @@
1210	1093	* to 1.8v. Please make sure the regulator framework is aware
1211	1094	* of your own regulator constraints
1212	1095	*/
1213		- return mmc_regulator_set_vqmmc(mmc, ios);
	1096	+ ret = mmc_regulator_set_vqmmc(mmc, ios);
	1097	+ return ret < 0 ? ret : 0;
1214	1098	}
1215	1099
1216	1100	/* no vqmmc regulator, assume fixed regulator at 3/3.3V */
..	..	@@ -1226,7 +1110,7 @@
1226	1110	.get_cd = meson_mmc_get_cd,
1227	1111	.pre_req = meson_mmc_pre_req,
1228	1112	.post_req = meson_mmc_post_req,
1229		- .execute_tuning = meson_mmc_execute_tuning,
	1113	+ .execute_tuning = meson_mmc_resampling_tuning,
1230	1114	.card_busy = meson_mmc_card_busy,
1231	1115	.start_signal_voltage_switch = meson_mmc_voltage_switch,
1232	1116	};
..	..	@@ -1238,7 +1122,7 @@
1238	1122	struct mmc_host *mmc;
1239	1123	int ret;
1240	1124
1241		- mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
	1125	+ mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct meson_host));
1242	1126	if (!mmc)
1243	1127	return -ENOMEM;
1244	1128	host = mmc_priv(mmc);
..	..	@@ -1246,62 +1130,41 @@
1246	1130	host->dev = &pdev->dev;
1247	1131	dev_set_drvdata(&pdev->dev, host);
1248	1132
1249		- spin_lock_init(&host->lock);
	1133	+ /* The G12A SDIO Controller needs an SRAM bounce buffer */
	1134	+ host->dram_access_quirk = device_property_read_bool(&pdev->dev,
	1135	+ "amlogic,dram-access-quirk");
1250	1136
1251	1137	/* Get regulators and the supported OCR mask */
1252	1138	host->vqmmc_enabled = false;
1253	1139	ret = mmc_regulator_get_supply(mmc);
1254	1140	if (ret)
1255		- goto free_host;
	1141	+ return ret;
1256	1142
1257	1143	ret = mmc_of_parse(mmc);
1258		- if (ret) {
1259		- if (ret != -EPROBE_DEFER)
1260		- dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1261		- goto free_host;
1262		- }
	1144	+ if (ret)
	1145	+ return dev_err_probe(&pdev->dev, ret, "error parsing DT\n");
1263	1146
1264	1147	host->data = (struct meson_mmc_data *)
1265	1148	of_device_get_match_data(&pdev->dev);
1266		- if (!host->data) {
1267		- ret = -EINVAL;
1268		- goto free_host;
1269		- }
	1149	+ if (!host->data)
	1150	+ return -EINVAL;
1270	1151
1271	1152	ret = device_reset_optional(&pdev->dev);
1272		- if (ret) {
1273		- if (ret != -EPROBE_DEFER)
1274		- dev_err(&pdev->dev, "device reset failed: %d\n", ret);
1275		-
1276		- return ret;
1277		- }
	1153	+ if (ret)
	1154	+ return dev_err_probe(&pdev->dev, ret, "device reset failed\n");
1278	1155
1279	1156	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1280	1157	host->regs = devm_ioremap_resource(&pdev->dev, res);
1281		- if (IS_ERR(host->regs)) {
1282		- ret = PTR_ERR(host->regs);
1283		- goto free_host;
1284		- }
	1158	+ if (IS_ERR(host->regs))
	1159	+ return PTR_ERR(host->regs);
1285	1160
1286	1161	host->irq = platform_get_irq(pdev, 0);
1287		- if (host->irq <= 0) {
1288		- dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1289		- ret = -EINVAL;
1290		- goto free_host;
1291		- }
	1162	+ if (host->irq < 0)
	1163	+ return host->irq;
1292	1164
1293	1165	host->pinctrl = devm_pinctrl_get(&pdev->dev);
1294		- if (IS_ERR(host->pinctrl)) {
1295		- ret = PTR_ERR(host->pinctrl);
1296		- goto free_host;
1297		- }
1298		-
1299		- host->pins_default = pinctrl_lookup_state(host->pinctrl,
1300		- PINCTRL_STATE_DEFAULT);
1301		- if (IS_ERR(host->pins_default)) {
1302		- ret = PTR_ERR(host->pins_default);
1303		- goto free_host;
1304		- }
	1166	+ if (IS_ERR(host->pinctrl))
	1167	+ return PTR_ERR(host->pinctrl);
1305	1168
1306	1169	host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1307	1170	"clk-gate");
..	..	@@ -1312,14 +1175,12 @@
1312	1175	}
1313	1176
1314	1177	host->core_clk = devm_clk_get(&pdev->dev, "core");
1315		- if (IS_ERR(host->core_clk)) {
1316		- ret = PTR_ERR(host->core_clk);
1317		- goto free_host;
1318		- }
	1178	+ if (IS_ERR(host->core_clk))
	1179	+ return PTR_ERR(host->core_clk);
1319	1180
1320	1181	ret = clk_prepare_enable(host->core_clk);
1321	1182	if (ret)
1322		- goto free_host;
	1183	+ return ret;
1323	1184
1324	1185	ret = meson_mmc_clk_init(host);
1325	1186	if (ret)
..	..	@@ -1339,26 +1200,54 @@
1339	1200	host->regs + SD_EMMC_IRQ_EN);
1340	1201
1341	1202	ret = request_threaded_irq(host->irq, meson_mmc_irq,
1342		- meson_mmc_irq_thread, IRQF_SHARED,
	1203	+ meson_mmc_irq_thread, IRQF_ONESHOT,
1343	1204	dev_name(&pdev->dev), host);
1344	1205	if (ret)
1345	1206	goto err_init_clk;
1346	1207
1347	1208	mmc->caps \|= MMC_CAP_CMD23;
1348		- mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
	1209	+ if (host->dram_access_quirk) {
	1210	+ /* Limit segments to 1 due to low available sram memory */
	1211	+ mmc->max_segs = 1;
	1212	+ /* Limit to the available sram memory */
	1213	+ mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
	1214	+ mmc->max_blk_size;
	1215	+ } else {
	1216	+ mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
	1217	+ mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
	1218	+ sizeof(struct sd_emmc_desc);
	1219	+ }
1349	1220	mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1350		- mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
1351	1221	mmc->max_seg_size = mmc->max_req_size;
1352	1222
1353		- /* data bounce buffer */
1354		- host->bounce_buf_size = mmc->max_req_size;
1355		- host->bounce_buf =
1356		- dma_alloc_coherent(host->dev, host->bounce_buf_size,
1357		- &host->bounce_dma_addr, GFP_KERNEL);
1358		- if (host->bounce_buf == NULL) {
1359		- dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1360		- ret = -ENOMEM;
1361		- goto err_free_irq;
	1223	+ /*
	1224	+ * At the moment, we don't know how to reliably enable HS400.
	1225	+ * From the different datasheets, it is not even clear if this mode
	1226	+ * is officially supported by any of the SoCs
	1227	+ */
	1228	+ mmc->caps2 &= ~MMC_CAP2_HS400;
	1229	+
	1230	+ if (host->dram_access_quirk) {
	1231	+ /*
	1232	+ * The MMC Controller embeds 1,5KiB of internal SRAM
	1233	+ * that can be used to be used as bounce buffer.
	1234	+ * In the case of the G12A SDIO controller, use these
	1235	+ * instead of the DDR memory
	1236	+ */
	1237	+ host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
	1238	+ host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
	1239	+ host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
	1240	+ } else {
	1241	+ /* data bounce buffer */
	1242	+ host->bounce_buf_size = mmc->max_req_size;
	1243	+ host->bounce_buf =
	1244	+ dma_alloc_coherent(host->dev, host->bounce_buf_size,
	1245	+ &host->bounce_dma_addr, GFP_KERNEL);
	1246	+ if (host->bounce_buf == NULL) {
	1247	+ dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
	1248	+ ret = -ENOMEM;
	1249	+ goto err_free_irq;
	1250	+ }
1362	1251	}
1363	1252
1364	1253	host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
..	..	@@ -1370,21 +1259,22 @@
1370	1259	}
1371	1260
1372	1261	mmc->ops = &meson_mmc_ops;
1373		- mmc_add_host(mmc);
	1262	+ ret = mmc_add_host(mmc);
	1263	+ if (ret)
	1264	+ goto err_free_irq;
1374	1265
1375	1266	return 0;
1376	1267
1377	1268	err_bounce_buf:
1378		- dma_free_coherent(host->dev, host->bounce_buf_size,
1379		- host->bounce_buf, host->bounce_dma_addr);
	1269	+ if (!host->dram_access_quirk)
	1270	+ dma_free_coherent(host->dev, host->bounce_buf_size,
	1271	+ host->bounce_buf, host->bounce_dma_addr);
1380	1272	err_free_irq:
1381	1273	free_irq(host->irq, host);
1382	1274	err_init_clk:
1383	1275	clk_disable_unprepare(host->mmc_clk);
1384	1276	err_core_clk:
1385	1277	clk_disable_unprepare(host->core_clk);
1386		-free_host:
1387		- mmc_free_host(mmc);
1388	1278	return ret;
1389	1279	}
1390	1280
..	..	@@ -1400,13 +1290,14 @@
1400	1290
1401	1291	dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1402	1292	host->descs, host->descs_dma_addr);
1403		- dma_free_coherent(host->dev, host->bounce_buf_size,
1404		- host->bounce_buf, host->bounce_dma_addr);
	1293	+
	1294	+ if (!host->dram_access_quirk)
	1295	+ dma_free_coherent(host->dev, host->bounce_buf_size,
	1296	+ host->bounce_buf, host->bounce_dma_addr);
1405	1297
1406	1298	clk_disable_unprepare(host->mmc_clk);
1407	1299	clk_disable_unprepare(host->core_clk);
1408	1300
1409		- mmc_free_host(host->mmc);
1410	1301	return 0;
1411	1302	}
1412	1303
..	..	@@ -1414,12 +1305,14 @@
1414	1305	.tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1415	1306	.rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1416	1307	.always_on = CLK_V2_ALWAYS_ON,
	1308	+ .adjust = SD_EMMC_ADJUST,
1417	1309	};
1418	1310
1419	1311	static const struct meson_mmc_data meson_axg_data = {
1420	1312	.tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1421	1313	.rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1422	1314	.always_on = CLK_V3_ALWAYS_ON,
	1315	+ .adjust = SD_EMMC_V3_ADJUST,
1423	1316	};
1424	1317
1425	1318	static const struct of_device_id meson_mmc_of_match[] = {
..	..	@@ -1437,6 +1330,7 @@
1437	1330	.remove = meson_mmc_remove,
1438	1331	.driver = {
1439	1332	.name = DRIVER_NAME,
	1333	+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1440	1334	.of_match_table = of_match_ptr(meson_mmc_of_match),
1441	1335	},
1442	1336	};