write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/mfd/rk630.c
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@@ -41,7 +41,7 @@
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 		dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
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 		return ret;
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 	}
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-	usleep_range(20, 30);
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+	udelay(20);
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45
 
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 	val = BIT(12 + 16);
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 	ret = regmap_write(rk630->cru, CRU_REG(0x50), val);
..
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@@ -49,7 +49,7 @@
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 		dev_err(rk630->dev, "Could not write to CRU: %d\n", ret);
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 		return ret;
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 	}
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-	usleep_range(20, 30);
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+	udelay(20);
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53
 
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 	/* power up && led*/
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 	val = BIT(1 + 16) | BIT(1) | BIT(2 + 16);
..
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@@ -113,14 +113,6 @@
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113
 
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 static const struct mfd_cell rk630_devs[] = {
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 	{
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-		.name = "rk630-efuse",
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-		.of_compatible = "rockchip,rk630-efuse",
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-	},
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-	{
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-		.name = "rk630-pinctrl",
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-		.of_compatible = "rockchip,rk630-pinctrl",
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-	},
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-	{
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 		.name = "rk630-tve",
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 		.of_compatible = "rockchip,rk630-tve",
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118
 	},
..
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@@ -131,10 +123,6 @@
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 	{
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 		.name = "rk630-macphy",
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 		.of_compatible = "rockchip,rk630-macphy",
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-	},
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-	{
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-		.name = "rk630-codec",
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-		.of_compatible = "rockchip,rk630-codec",
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 	},
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127
 };
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128
 
..
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@@ -170,27 +158,6 @@
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 };
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 EXPORT_SYMBOL_GPL(rk630_grf_regmap_config);
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160
 
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-static const struct regmap_range rk630_pinctrl_readable_ranges[] = {
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-	regmap_reg_range(GPIO0_BASE, GPIO0_BASE + GPIO_VER_ID),
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-	regmap_reg_range(GPIO1_BASE, GPIO1_BASE + GPIO_VER_ID),
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-};
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-
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-static const struct regmap_access_table rk630_pinctrl_readable_table = {
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-	.yes_ranges = rk630_pinctrl_readable_ranges,
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-	.n_yes_ranges = ARRAY_SIZE(rk630_pinctrl_readable_ranges),
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-};
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-
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-const struct regmap_config rk630_pinctrl_regmap_config = {
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-	.name = "pinctrl",
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-	.reg_bits = 32,
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-	.val_bits = 32,
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-	.reg_stride = 4,
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-	.max_register = GPIO_MAX_REGISTER,
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-	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
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-	.val_format_endian = REGMAP_ENDIAN_NATIVE,
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-	.rd_table = &rk630_pinctrl_readable_table,
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-};
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-
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161
 static const struct regmap_range rk630_cru_readable_ranges[] = {
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 	regmap_reg_range(CRU_SPLL_CON0, CRU_SPLL_CON2),
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 	regmap_reg_range(CRU_MODE_CON, CRU_MODE_CON),
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@@ -214,6 +181,7 @@
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 	.val_format_endian = REGMAP_ENDIAN_NATIVE,
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 	.rd_table = &rk630_cru_readable_table,
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183
 };
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+EXPORT_SYMBOL_GPL(rk630_cru_regmap_config);
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185
 
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 static const struct regmap_range rk630_rtc_readable_ranges[] = {
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 	regmap_reg_range(RTC_SET_SECONDS, RTC_CNT_3),
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@@ -234,29 +202,36 @@
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 	.val_format_endian = REGMAP_ENDIAN_NATIVE,
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 	.rd_table = &rk630_rtc_readable_table,
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 };
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+EXPORT_SYMBOL_GPL(rk630_rtc_regmap_config);
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206
 
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 int rk630_core_probe(struct rk630 *rk630)
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 {
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 	bool macphy_enabled = false;
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+	struct clk *ref_clk;
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 	struct device_node *np;
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212
 	unsigned long rate;
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213
 	int ret;
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214
 
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-	rk630->ref_clk = devm_clk_get(rk630->dev, "ref");
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-	if (IS_ERR(rk630->ref_clk)) {
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-		dev_err(rk630->dev, "failed to get ref clk source\n");
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-		return PTR_ERR(rk630->ref_clk);
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+	if (!rk630->irq) {
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+		dev_err(rk630->dev, "No interrupt support, no core IRQ\n");
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+		return -EINVAL;
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218
 	}
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219
 
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-	ret = clk_prepare_enable(rk630->ref_clk);
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+	ref_clk = devm_clk_get(rk630->dev, "ref");
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+	if (IS_ERR(ref_clk)) {
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+		dev_err(rk630->dev, "failed to get ref clk source\n");
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+		return PTR_ERR(ref_clk);
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+	}
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+
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+	ret = clk_prepare_enable(ref_clk);
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 	if (ret < 0) {
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 		dev_err(rk630->dev, "failed to enable ref clk - %d\n", ret);
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 		return ret;
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230
 	}
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-	rate = clk_get_rate(rk630->ref_clk);
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+	rate = clk_get_rate(ref_clk);
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232
 
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 	ret = devm_add_action_or_reset(rk630->dev, (void (*) (void *))clk_disable_unprepare,
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-				       rk630->ref_clk);
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+				       ref_clk);
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 	if (ret)
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 		return ret;
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237
 
..
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@@ -273,11 +248,10 @@
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248
 	usleep_range(50000, 60000);
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249
 	gpiod_direction_output(rk630->reset_gpio, 0);
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250
 
276
-	if (!rk630->irq) {
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-		dev_err(rk630->dev, "No interrupt support, no core IRQ\n");
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-		return -EINVAL;
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-	}
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-
251
+	/**
252
+	 * If rtc output clamp is enabled, rtc regs can't be accessed,
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+	 * RK630 irq add will failed.
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+	 */
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255
 	regmap_update_bits(rk630->grf, PLUMAGE_GRF_SOC_CON0,
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 			   RTC_CLAMP_EN_MASK, RTC_CLAMP_EN(1));
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