write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/mfd/intel_soc_pmic_crc.c
..
..
@@ -1,25 +1,18 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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- * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
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+ * Device access for Crystal Cove PMIC
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  *
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  * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License version
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- * 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  *
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  * Author: Yang, Bin <bin.yang@intel.com>
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  * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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  */
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-#include <linux/mfd/core.h>
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 #include <linux/interrupt.h>
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 #include <linux/regmap.h>
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+#include <linux/mfd/core.h>
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 #include <linux/mfd/intel_soc_pmic.h>
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+
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 #include "intel_soc_pmic_core.h"
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 #define CRYSTAL_COVE_MAX_REGISTER	0xC6
..
..
@@ -36,48 +29,23 @@
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 #define CRYSTAL_COVE_IRQ_VHDMIOCP	6
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 static struct resource gpio_resources[] = {
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-	{
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-		.name	= "GPIO",
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-		.start	= CRYSTAL_COVE_IRQ_GPIO,
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-		.end	= CRYSTAL_COVE_IRQ_GPIO,
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-		.flags	= IORESOURCE_IRQ,
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-	},
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+	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
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 };
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 static struct resource pwrsrc_resources[] = {
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-	{
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-		.name  = "PWRSRC",
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-		.start = CRYSTAL_COVE_IRQ_PWRSRC,
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-		.end   = CRYSTAL_COVE_IRQ_PWRSRC,
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-		.flags = IORESOURCE_IRQ,
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-	},
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+	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
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 };
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 static struct resource adc_resources[] = {
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-	{
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-		.name  = "ADC",
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-		.start = CRYSTAL_COVE_IRQ_ADC,
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-		.end   = CRYSTAL_COVE_IRQ_ADC,
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-		.flags = IORESOURCE_IRQ,
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-	},
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+	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
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 };
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 static struct resource thermal_resources[] = {
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-	{
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-		.name  = "THERMAL",
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-		.start = CRYSTAL_COVE_IRQ_THRM,
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-		.end   = CRYSTAL_COVE_IRQ_THRM,
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-		.flags = IORESOURCE_IRQ,
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-	},
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+	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
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 };
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 static struct resource bcu_resources[] = {
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-	{
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-		.name  = "BCU",
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-		.start = CRYSTAL_COVE_IRQ_BCU,
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-		.end   = CRYSTAL_COVE_IRQ_BCU,
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-		.flags = IORESOURCE_IRQ,
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-	},
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+	DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
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 };
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 static struct mfd_cell crystal_cove_byt_dev[] = {
..
..
@@ -107,7 +75,7 @@
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 		.resources = gpio_resources,
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 	},
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 	{
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-		.name = "crystal_cove_pmic",
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+		.name = "byt_crystal_cove_pmic",
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 	},
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 	{
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 		.name = "crystal_cove_pwm",
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@@ -119,6 +87,9 @@
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 		.name = "crystal_cove_gpio",
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 		.num_resources = ARRAY_SIZE(gpio_resources),
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 		.resources = gpio_resources,
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+	},
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+	{
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+		.name = "cht_crystal_cove_pmic",
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 	},
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 	{
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 		.name = "crystal_cove_pwm",
..
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@@ -134,27 +105,13 @@
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 };
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 static const struct regmap_irq crystal_cove_irqs[] = {
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-	[CRYSTAL_COVE_IRQ_PWRSRC] = {
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-		.mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
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-	},
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-	[CRYSTAL_COVE_IRQ_THRM] = {
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-		.mask = BIT(CRYSTAL_COVE_IRQ_THRM),
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-	},
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-	[CRYSTAL_COVE_IRQ_BCU] = {
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-		.mask = BIT(CRYSTAL_COVE_IRQ_BCU),
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-	},
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-	[CRYSTAL_COVE_IRQ_ADC] = {
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-		.mask = BIT(CRYSTAL_COVE_IRQ_ADC),
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-	},
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-	[CRYSTAL_COVE_IRQ_CHGR] = {
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-		.mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
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-	},
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-	[CRYSTAL_COVE_IRQ_GPIO] = {
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-		.mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
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-	},
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-	[CRYSTAL_COVE_IRQ_VHDMIOCP] = {
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-		.mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
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-	},
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+	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
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+	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
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+	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
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+	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
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+	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
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+	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
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+	REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
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 };
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 static const struct regmap_irq_chip crystal_cove_irq_chip = {