write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/memory/fsl_ifc.c
..
..
@@ -1,23 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
1
2
 /*
2
3
  * Copyright 2011 Freescale Semiconductor, Inc
3
4
  *
4
5
  * Freescale Integrated Flash Controller
5
6
  *
6
7
  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7
- *
8
- * This program is free software; you can redistribute  it and/or modify it
9
- * under  the terms of  the GNU General  Public License as published by the
10
- * Free Software Foundation;  either version 2 of the  License, or (at your
11
- * option) any later version.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
- * GNU General Public License for more details.
17
- *
18
- * You should have received a copy of the GNU General Public License
19
- * along with this program; if not, write to the Free Software
20
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
8
  */
22
9
 #include <linux/module.h>
23
10
 #include <linux/kernel.h>
..
..
@@ -66,6 +53,7 @@
66
53
 
67
54
 	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
68
55
 		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
56
+
69
57
 		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
70
58
 				convert_ifc_address(addr_base))
71
59
 			return i;
..
..
@@ -165,8 +153,8 @@
165
153
 	/* read for chip select error */
166
154
 	cs_err = ifc_in32(&ifc->cm_evter_stat);
167
155
 	if (cs_err) {
168
-		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
169
-				"any memory bank 0x%08X\n", cs_err);
156
+		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to any memory bank 0x%08X\n",
157
+			cs_err);
170
158
 		/* clear the chip select error */
171
159
 		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
172
160
 
..
..
@@ -175,24 +163,24 @@
175
163
 		err_addr = ifc_in32(&ifc->cm_erattr1);
176
164
 
177
165
 		if (status & IFC_CM_ERATTR0_ERTYP_READ)
178
-			dev_err(ctrl->dev, "Read transaction error"
179
-				"CM_ERATTR0 0x%08X\n", status);
166
+			dev_err(ctrl->dev, "Read transaction error CM_ERATTR0 0x%08X\n",
167
+				status);
180
168
 		else
181
-			dev_err(ctrl->dev, "Write transaction error"
182
-				"CM_ERATTR0 0x%08X\n", status);
169
+			dev_err(ctrl->dev, "Write transaction error CM_ERATTR0 0x%08X\n",
170
+				status);
183
171
 
184
172
 		err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
185
173
 					IFC_CM_ERATTR0_ERAID_SHIFT;
186
-		dev_err(ctrl->dev, "AXI ID of the error"
187
-					"transaction 0x%08X\n", err_axiid);
174
+		dev_err(ctrl->dev, "AXI ID of the error transaction 0x%08X\n",
175
+			err_axiid);
188
176
 
189
177
 		err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
190
178
 					IFC_CM_ERATTR0_ESRCID_SHIFT;
191
-		dev_err(ctrl->dev, "SRC ID of the error"
192
-					"transaction 0x%08X\n", err_srcid);
179
+		dev_err(ctrl->dev, "SRC ID of the error transaction 0x%08X\n",
180
+			err_srcid);
193
181
 
194
-		dev_err(ctrl->dev, "Transaction Address corresponding to error"
195
-					"ERADDR 0x%08X\n", err_addr);
182
+		dev_err(ctrl->dev, "Transaction Address corresponding to error ERADDR 0x%08X\n",
183
+			err_addr);
196
184
 
197
185
 		ret = IRQ_HANDLED;
198
186
 	}
..
..
@@ -211,7 +199,7 @@
211
199
  * the resources needed for the controller only.  The
212
200
  * resources for the NAND banks themselves are allocated
213
201
  * in the chip probe function.
214
-*/
202
+ */
215
203
 static int fsl_ifc_ctrl_probe(struct platform_device *dev)
216
204
 {
217
205
 	int ret = 0;
..
..
@@ -262,8 +250,7 @@
262
250
 	/* get the Controller level irq */
263
251
 	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
264
252
 	if (fsl_ifc_ctrl_dev->irq == 0) {
265
-		dev_err(&dev->dev, "failed to get irq resource "
266
-							"for IFC\n");
253
+		dev_err(&dev->dev, "failed to get irq resource for IFC\n");
267
254
 		ret = -ENODEV;
268
255
 		goto err;
269
256
 	}