write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/irqchip/irq-xtensa-mx.c
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@@ -62,7 +62,7 @@
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 	__this_cpu_write(cached_irq_mask,
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 			XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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 			XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
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-	set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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+	xtensa_set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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 			XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
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 }
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@@ -71,14 +71,17 @@
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 	unsigned int mask = 1u << d->hwirq;
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 	if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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-				XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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-		set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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-					HW_IRQ_MX_BASE), MIENG);
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-	} else {
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-		mask = __this_cpu_read(cached_irq_mask) & ~mask;
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-		__this_cpu_write(cached_irq_mask, mask);
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-		set_sr(mask, intenable);
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+		    XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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+		unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
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+
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+		if (ext_irq >= HW_IRQ_MX_BASE) {
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+			set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG);
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+			return;
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+		}
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 	}
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+	mask = __this_cpu_read(cached_irq_mask) & ~mask;
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+	__this_cpu_write(cached_irq_mask, mask);
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+	xtensa_set_sr(mask, intenable);
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 }
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 static void xtensa_mx_irq_unmask(struct irq_data *d)
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@@ -86,14 +89,17 @@
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 	unsigned int mask = 1u << d->hwirq;
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 	if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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-				XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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-		set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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-					HW_IRQ_MX_BASE), MIENGSET);
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-	} else {
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-		mask |= __this_cpu_read(cached_irq_mask);
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-		__this_cpu_write(cached_irq_mask, mask);
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-		set_sr(mask, intenable);
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+		    XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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+		unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
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+
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+		if (ext_irq >= HW_IRQ_MX_BASE) {
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+			set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET);
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+			return;
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+		}
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 	}
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+	mask |= __this_cpu_read(cached_irq_mask);
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+	__this_cpu_write(cached_irq_mask, mask);
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+	xtensa_set_sr(mask, intenable);
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 }
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 static void xtensa_mx_irq_enable(struct irq_data *d)
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@@ -108,12 +114,16 @@
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 static void xtensa_mx_irq_ack(struct irq_data *d)
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 {
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-	set_sr(1 << d->hwirq, intclear);
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+	xtensa_set_sr(1 << d->hwirq, intclear);
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 }
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 static int xtensa_mx_irq_retrigger(struct irq_data *d)
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 {
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-	set_sr(1 << d->hwirq, intset);
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+	unsigned int mask = 1u << d->hwirq;
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+
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+	if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
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+		return 0;
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+	xtensa_set_sr(mask, intset);
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 	return 1;
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 }
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@@ -141,14 +151,25 @@
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 	.irq_set_affinity = xtensa_mx_irq_set_affinity,
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 };
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+static void __init xtensa_mx_init_common(struct irq_domain *root_domain)
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+{
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+	unsigned int i;
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+
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+	irq_set_default_host(root_domain);
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+	secondary_init_irq();
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+
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+	/* Initialize default IRQ routing to CPU 0 */
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+	for (i = 0; i < XCHAL_NUM_EXTINTERRUPTS; ++i)
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+		set_er(1, MIROUT(i));
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+}
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+
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 int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
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 {
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 	struct irq_domain *root_domain =
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 		irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
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 				&xtensa_mx_irq_domain_ops,
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 				&xtensa_mx_irq_chip);
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-	irq_set_default_host(root_domain);
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-	secondary_init_irq();
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+	xtensa_mx_init_common(root_domain);
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 	return 0;
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 }
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@@ -158,8 +179,7 @@
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 	struct irq_domain *root_domain =
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 		irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
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 				&xtensa_mx_irq_chip);
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-	irq_set_default_host(root_domain);
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-	secondary_init_irq();
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+	xtensa_mx_init_common(root_domain);
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 	return 0;
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 }
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 IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);