write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/irqchip/irq-xilinx-intc.c
..
..
@@ -38,29 +38,31 @@
38
38
 	void		__iomem *base;
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39
 	struct		irq_domain *root_domain;
40
40
 	u32		intr_mask;
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+	u32		nr_irq;
41
42
 };
42
43
 
43
-static struct xintc_irq_chip *xintc_irqc;
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+static struct xintc_irq_chip *primary_intc;
44
45
 
45
-static void xintc_write(int reg, u32 data)
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+static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
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47
 {
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48
 	if (static_branch_unlikely(&xintc_is_be))
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-		iowrite32be(data, xintc_irqc->base + reg);
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+		iowrite32be(data, irqc->base + reg);
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 	else
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-		iowrite32(data, xintc_irqc->base + reg);
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+		iowrite32(data, irqc->base + reg);
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52
 }
52
53
 
53
-static unsigned int xintc_read(int reg)
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+static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
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 {
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 	if (static_branch_unlikely(&xintc_is_be))
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-		return ioread32be(xintc_irqc->base + reg);
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+		return ioread32be(irqc->base + reg);
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 	else
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-		return ioread32(xintc_irqc->base + reg);
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+		return ioread32(irqc->base + reg);
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60
 }
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61
 
61
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 static void intc_enable_or_unmask(struct irq_data *d)
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63
 {
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-	unsigned long mask = 1 << d->hwirq;
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+	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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+	unsigned long mask = BIT(d->hwirq);
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66
 
65
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 	pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
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68
 
..
..
@@ -69,30 +71,35 @@
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71
 	 * acks the irq before calling the interrupt handler
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72
 	 */
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 	if (irqd_is_level_type(d))
72
-		xintc_write(IAR, mask);
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+		xintc_write(irqc, IAR, mask);
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75
 
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-	xintc_write(SIE, mask);
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+	xintc_write(irqc, SIE, mask);
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77
 }
76
78
 
77
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 static void intc_disable_or_mask(struct irq_data *d)
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80
 {
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+	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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+
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 	pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
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-	xintc_write(CIE, 1 << d->hwirq);
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+	xintc_write(irqc, CIE, BIT(d->hwirq));
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 }
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86
 
83
87
 static void intc_ack(struct irq_data *d)
84
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 {
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+	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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+
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 	pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
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-	xintc_write(IAR, 1 << d->hwirq);
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+	xintc_write(irqc, IAR, BIT(d->hwirq));
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 }
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94
 
89
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 static void intc_mask_ack(struct irq_data *d)
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 {
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-	unsigned long mask = 1 << d->hwirq;
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+	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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+	unsigned long mask = BIT(d->hwirq);
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99
 
93
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 	pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
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-	xintc_write(CIE, mask);
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-	xintc_write(IAR, mask);
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+	xintc_write(irqc, CIE, mask);
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+	xintc_write(irqc, IAR, mask);
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103
 }
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104
 
98
105
 static struct irq_chip intc_dev = {
..
..
@@ -103,13 +110,28 @@
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110
 	.irq_mask_ack = intc_mask_ack,
104
111
 };
105
112
 
113
+static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc)
114
+{
115
+	unsigned int irq = 0;
116
+	u32 hwirq;
117
+
118
+	hwirq = xintc_read(irqc, IVR);
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+	if (hwirq != -1U)
120
+		irq = irq_find_mapping(irqc->root_domain, hwirq);
121
+
122
+	pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
123
+
124
+	return irq;
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+}
126
+
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127
 unsigned int xintc_get_irq(void)
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128
 {
108
-	unsigned int hwirq, irq = -1;
129
+	unsigned int irq = -1;
130
+	u32 hwirq;
109
131
 
110
-	hwirq = xintc_read(IVR);
132
+	hwirq = xintc_read(primary_intc, IVR);
111
133
 	if (hwirq != -1U)
112
-		irq = irq_find_mapping(xintc_irqc->root_domain, hwirq);
134
+		irq = irq_find_mapping(primary_intc->root_domain, hwirq);
113
135
 
114
136
 	pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
115
137
 
..
..
@@ -118,15 +140,18 @@
118
140
 
119
141
 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
120
142
 {
121
-	if (xintc_irqc->intr_mask & (1 << hw)) {
143
+	struct xintc_irq_chip *irqc = d->host_data;
144
+
145
+	if (irqc->intr_mask & BIT(hw)) {
122
146
 		irq_set_chip_and_handler_name(irq, &intc_dev,
123
-						handle_edge_irq, "edge");
147
+					      handle_edge_irq, "edge");
124
148
 		irq_clear_status_flags(irq, IRQ_LEVEL);
125
149
 	} else {
126
150
 		irq_set_chip_and_handler_name(irq, &intc_dev,
127
-						handle_level_irq, "level");
151
+					      handle_level_irq, "level");
128
152
 		irq_set_status_flags(irq, IRQ_LEVEL);
129
153
 	}
154
+	irq_set_chip_data(irq, irqc);
130
155
 	return 0;
131
156
 }
132
157
 
..
..
@@ -138,12 +163,14 @@
138
163
 static void xil_intc_irq_handler(struct irq_desc *desc)
139
164
 {
140
165
 	struct irq_chip *chip = irq_desc_get_chip(desc);
166
+	struct xintc_irq_chip *irqc;
141
167
 	u32 pending;
142
168
 
169
+	irqc = irq_data_get_irq_handler_data(&desc->irq_data);
143
170
 	chained_irq_enter(chip, desc);
144
171
 	do {
145
-		pending = xintc_get_irq();
146
-		if (pending == -1U)
172
+		pending = xintc_get_irq_local(irqc);
173
+		if (pending == 0)
147
174
 			break;
148
175
 		generic_handle_irq(pending);
149
176
 	} while (true);
..
..
@@ -153,28 +180,19 @@
153
180
 static int __init xilinx_intc_of_init(struct device_node *intc,
154
181
 					     struct device_node *parent)
155
182
 {
156
-	u32 nr_irq;
157
-	int ret, irq;
158
183
 	struct xintc_irq_chip *irqc;
159
-
160
-	if (xintc_irqc) {
161
-		pr_err("irq-xilinx: Multiple instances aren't supported\n");
162
-		return -EINVAL;
163
-	}
184
+	int ret, irq;
164
185
 
165
186
 	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
166
187
 	if (!irqc)
167
188
 		return -ENOMEM;
168
-
169
-	xintc_irqc = irqc;
170
-
171
189
 	irqc->base = of_iomap(intc, 0);
172
190
 	BUG_ON(!irqc->base);
173
191
 
174
-	ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq);
192
+	ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
175
193
 	if (ret < 0) {
176
194
 		pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
177
-		goto err_alloc;
195
+		goto error;
178
196
 	}
179
197
 
180
198
 	ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
..
..
@@ -183,34 +201,35 @@
183
201
 		irqc->intr_mask = 0;
184
202
 	}
185
203
 
186
-	if (irqc->intr_mask >> nr_irq)
204
+	if (irqc->intr_mask >> irqc->nr_irq)
187
205
 		pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
188
206
 
189
207
 	pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
190
-		intc, nr_irq, irqc->intr_mask);
208
+		intc, irqc->nr_irq, irqc->intr_mask);
191
209
 
192
210
 
193
211
 	/*
194
212
 	 * Disable all external interrupts until they are
195
-	 * explicity requested.
213
+	 * explicitly requested.
196
214
 	 */
197
-	xintc_write(IER, 0);
215
+	xintc_write(irqc, IER, 0);
198
216
 
199
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 	/* Acknowledge any pending interrupts just in case. */
200
-	xintc_write(IAR, 0xffffffff);
218
+	xintc_write(irqc, IAR, 0xffffffff);
201
219
 
202
220
 	/* Turn on the Master Enable. */
203
-	xintc_write(MER, MER_HIE | MER_ME);
204
-	if (!(xintc_read(MER) & (MER_HIE | MER_ME))) {
221
+	xintc_write(irqc, MER, MER_HIE | MER_ME);
222
+	if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
205
223
 		static_branch_enable(&xintc_is_be);
206
-		xintc_write(MER, MER_HIE | MER_ME);
224
+		xintc_write(irqc, MER, MER_HIE | MER_ME);
207
225
 	}
208
226
 
209
-	irqc->root_domain = irq_domain_add_linear(intc, nr_irq,
227
+	irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
210
228
 						  &xintc_irq_domain_ops, irqc);
211
229
 	if (!irqc->root_domain) {
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230
 		pr_err("irq-xilinx: Unable to create IRQ domain\n");
213
-		goto err_alloc;
231
+		ret = -EINVAL;
232
+		goto error;
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233
 	}
215
234
 
216
235
 	if (parent) {
..
..
@@ -222,16 +241,17 @@
222
241
 		} else {
223
242
 			pr_err("irq-xilinx: interrupts property not in DT\n");
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243
 			ret = -EINVAL;
225
-			goto err_alloc;
244
+			goto error;
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245
 		}
227
246
 	} else {
228
-		irq_set_default_host(irqc->root_domain);
247
+		primary_intc = irqc;
248
+		irq_set_default_host(primary_intc->root_domain);
229
249
 	}
230
250
 
231
251
 	return 0;
232
252
 
233
-err_alloc:
234
-	xintc_irqc = NULL;
253
+error:
254
+	iounmap(irqc->base);
235
255
 	kfree(irqc);
236
256
 	return ret;
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257