write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/irqchip/irq-tegra.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Driver code for Tegra's Legacy Interrupt Controller
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  *
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@@ -10,16 +11,6 @@
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  *	Colin Cross <ccross@android.com>
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  *
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  * Copyright (C) 2010,2013, NVIDIA Corporation
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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  */
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 #include <linux/io.h>
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@@ -157,10 +148,10 @@
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 		lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
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 		/* Disable COP interrupts */
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-		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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+		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
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 		/* Disable CPU interrupts */
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-		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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+		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
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 		/* Enable the wakeup sources of ictlr */
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 		writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
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@@ -181,12 +172,12 @@
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 		writel_relaxed(lic->cpu_iep[i],
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 			       ictlr + ICTLR_CPU_IEP_CLASS);
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-		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
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+		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
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 		writel_relaxed(lic->cpu_ier[i],
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 			       ictlr + ICTLR_CPU_IER_SET);
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 		writel_relaxed(lic->cop_iep[i],
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 			       ictlr + ICTLR_COP_IEP_CLASS);
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-		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
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+		writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
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 		writel_relaxed(lic->cop_ier[i],
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 			       ictlr + ICTLR_COP_IER_SET);
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 	}
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@@ -321,7 +312,7 @@
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 		lic->base[i] = base;
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 		/* Disable all interrupts */
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-		writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
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+		writel_relaxed(GENMASK(31, 0), base + ICTLR_CPU_IER_CLR);
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 		/* All interrupts target IRQ */
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 		writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
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