forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/irqchip/irq-stm32-exti.c
....@@ -6,19 +6,25 @@
66  */
77 
88 #include <linux/bitops.h>
9
+#include <linux/delay.h>
10
+#include <linux/hwspinlock.h>
911 #include <linux/interrupt.h>
1012 #include <linux/io.h>
1113 #include <linux/irq.h>
1214 #include <linux/irqchip.h>
1315 #include <linux/irqchip/chained_irq.h>
1416 #include <linux/irqdomain.h>
17
+#include <linux/module.h>
1518 #include <linux/of_address.h>
1619 #include <linux/of_irq.h>
20
+#include <linux/of_platform.h>
1721 #include <linux/syscore_ops.h>
1822 
1923 #include <dt-bindings/interrupt-controller/arm-gic.h>
2024 
2125 #define IRQS_PER_BANK 32
26
+
27
+#define HWSPNLCK_TIMEOUT	1000 /* usec */
2228 
2329 struct stm32_exti_bank {
2430 	u32 imr_ofst;
....@@ -35,6 +41,7 @@
3541 struct stm32_desc_irq {
3642 	u32 exti;
3743 	u32 irq_parent;
44
+	struct irq_chip *chip;
3845 };
3946 
4047 struct stm32_exti_drv_data {
....@@ -58,6 +65,7 @@
5865 	void __iomem *base;
5966 	struct stm32_exti_chip_data *chips_data;
6067 	const struct stm32_exti_drv_data *drv_data;
68
+	struct hwspinlock *hwlock;
6169 };
6270 
6371 static struct stm32_exti_host_data *stm32_host_data;
....@@ -158,27 +166,45 @@
158166 	&stm32mp1_exti_b3,
159167 };
160168 
169
+static struct irq_chip stm32_exti_h_chip;
170
+static struct irq_chip stm32_exti_h_chip_direct;
171
+
161172 static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
162
-	{ .exti = 0, .irq_parent = 6 },
163
-	{ .exti = 1, .irq_parent = 7 },
164
-	{ .exti = 2, .irq_parent = 8 },
165
-	{ .exti = 3, .irq_parent = 9 },
166
-	{ .exti = 4, .irq_parent = 10 },
167
-	{ .exti = 5, .irq_parent = 23 },
168
-	{ .exti = 6, .irq_parent = 64 },
169
-	{ .exti = 7, .irq_parent = 65 },
170
-	{ .exti = 8, .irq_parent = 66 },
171
-	{ .exti = 9, .irq_parent = 67 },
172
-	{ .exti = 10, .irq_parent = 40 },
173
-	{ .exti = 11, .irq_parent = 42 },
174
-	{ .exti = 12, .irq_parent = 76 },
175
-	{ .exti = 13, .irq_parent = 77 },
176
-	{ .exti = 14, .irq_parent = 121 },
177
-	{ .exti = 15, .irq_parent = 127 },
178
-	{ .exti = 16, .irq_parent = 1 },
179
-	{ .exti = 65, .irq_parent = 144 },
180
-	{ .exti = 68, .irq_parent = 143 },
181
-	{ .exti = 73, .irq_parent = 129 },
173
+	{ .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
174
+	{ .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
175
+	{ .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
176
+	{ .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
177
+	{ .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
178
+	{ .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
179
+	{ .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
180
+	{ .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
181
+	{ .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
182
+	{ .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
183
+	{ .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
184
+	{ .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
185
+	{ .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
186
+	{ .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
187
+	{ .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
188
+	{ .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
189
+	{ .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
190
+	{ .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
191
+	{ .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
192
+	{ .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
193
+	{ .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
194
+	{ .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
195
+	{ .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
196
+	{ .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
197
+	{ .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
198
+	{ .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
199
+	{ .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
200
+	{ .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
201
+	{ .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
202
+	{ .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
203
+	{ .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
204
+	{ .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
205
+	{ .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
206
+	{ .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
207
+	{ .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
182208 };
183209 
184210 static const struct stm32_exti_drv_data stm32mp1_drv_data = {
....@@ -188,22 +214,23 @@
188214 	.irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
189215 };
190216 
191
-static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
192
-			     irq_hw_number_t hwirq)
217
+static const struct
218
+stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
219
+				    irq_hw_number_t hwirq)
193220 {
194
-	const struct stm32_desc_irq *desc_irq;
221
+	const struct stm32_desc_irq *desc = NULL;
195222 	int i;
196223 
197224 	if (!drv_data->desc_irqs)
198
-		return -EINVAL;
225
+		return NULL;
199226 
200227 	for (i = 0; i < drv_data->irq_nr; i++) {
201
-		desc_irq = &drv_data->desc_irqs[i];
202
-		if (desc_irq->exti == hwirq)
203
-			return desc_irq->irq_parent;
228
+		desc = &drv_data->desc_irqs[i];
229
+		if (desc->exti == hwirq)
230
+			break;
204231 	}
205232 
206
-	return -EINVAL;
233
+	return desc;
207234 }
208235 
209236 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
....@@ -274,26 +301,37 @@
274301 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
275302 	struct stm32_exti_chip_data *chip_data = gc->private;
276303 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
304
+	struct hwspinlock *hwlock = chip_data->host_data->hwlock;
277305 	u32 rtsr, ftsr;
278306 	int err;
279307 
280308 	irq_gc_lock(gc);
281309 
310
+	if (hwlock) {
311
+		err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
312
+		if (err) {
313
+			pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
314
+			goto unlock;
315
+		}
316
+	}
317
+
282318 	rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
283319 	ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
284320 
285321 	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
286
-	if (err) {
287
-		irq_gc_unlock(gc);
288
-		return err;
289
-	}
322
+	if (err)
323
+		goto unspinlock;
290324 
291325 	irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
292326 	irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
293327 
328
+unspinlock:
329
+	if (hwlock)
330
+		hwspin_unlock_in_atomic(hwlock);
331
+unlock:
294332 	irq_gc_unlock(gc);
295333 
296
-	return 0;
334
+	return err;
297335 }
298336 
299337 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
....@@ -465,25 +503,38 @@
465503 {
466504 	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
467505 	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
506
+	struct hwspinlock *hwlock = chip_data->host_data->hwlock;
468507 	void __iomem *base = chip_data->host_data->base;
469508 	u32 rtsr, ftsr;
470509 	int err;
471510 
472511 	raw_spin_lock(&chip_data->rlock);
512
+
513
+	if (hwlock) {
514
+		err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
515
+		if (err) {
516
+			pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
517
+			goto unlock;
518
+		}
519
+	}
520
+
473521 	rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
474522 	ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
475523 
476524 	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
477
-	if (err) {
478
-		raw_spin_unlock(&chip_data->rlock);
479
-		return err;
480
-	}
525
+	if (err)
526
+		goto unspinlock;
481527 
482528 	writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
483529 	writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
530
+
531
+unspinlock:
532
+	if (hwlock)
533
+		hwspin_unlock_in_atomic(hwlock);
534
+unlock:
484535 	raw_spin_unlock(&chip_data->rlock);
485536 
486
-	return 0;
537
+	return err;
487538 }
488539 
489540 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
....@@ -512,8 +563,7 @@
512563 	return -EINVAL;
513564 }
514565 
515
-#ifdef CONFIG_PM
516
-static int stm32_exti_h_suspend(void)
566
+static int __maybe_unused stm32_exti_h_suspend(void)
517567 {
518568 	struct stm32_exti_chip_data *chip_data;
519569 	int i;
....@@ -528,7 +578,7 @@
528578 	return 0;
529579 }
530580 
531
-static void stm32_exti_h_resume(void)
581
+static void __maybe_unused stm32_exti_h_resume(void)
532582 {
533583 	struct stm32_exti_chip_data *chip_data;
534584 	int i;
....@@ -542,28 +592,58 @@
542592 }
543593 
544594 static struct syscore_ops stm32_exti_h_syscore_ops = {
595
+#ifdef CONFIG_PM_SLEEP
545596 	.suspend	= stm32_exti_h_suspend,
546597 	.resume		= stm32_exti_h_resume,
598
+#endif
547599 };
548600 
549
-static void stm32_exti_h_syscore_init(void)
601
+static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
550602 {
603
+	stm32_host_data = host_data;
551604 	register_syscore_ops(&stm32_exti_h_syscore_ops);
552605 }
553
-#else
554
-static inline void stm32_exti_h_syscore_init(void) {}
555
-#endif
606
+
607
+static void stm32_exti_h_syscore_deinit(void)
608
+{
609
+	unregister_syscore_ops(&stm32_exti_h_syscore_ops);
610
+}
611
+
612
+static int stm32_exti_h_retrigger(struct irq_data *d)
613
+{
614
+	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
615
+	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
616
+	void __iomem *base = chip_data->host_data->base;
617
+	u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
618
+
619
+	writel_relaxed(mask, base + stm32_bank->swier_ofst);
620
+
621
+	return 0;
622
+}
556623 
557624 static struct irq_chip stm32_exti_h_chip = {
558625 	.name			= "stm32-exti-h",
559626 	.irq_eoi		= stm32_exti_h_eoi,
560627 	.irq_mask		= stm32_exti_h_mask,
561628 	.irq_unmask		= stm32_exti_h_unmask,
562
-	.irq_retrigger		= irq_chip_retrigger_hierarchy,
629
+	.irq_retrigger		= stm32_exti_h_retrigger,
563630 	.irq_set_type		= stm32_exti_h_set_type,
564631 	.irq_set_wake		= stm32_exti_h_set_wake,
565632 	.flags			= IRQCHIP_MASK_ON_SUSPEND,
566633 	.irq_set_affinity	= IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
634
+};
635
+
636
+static struct irq_chip stm32_exti_h_chip_direct = {
637
+	.name			= "stm32-exti-h-direct",
638
+	.irq_eoi		= irq_chip_eoi_parent,
639
+	.irq_ack		= irq_chip_ack_parent,
640
+	.irq_mask		= irq_chip_mask_parent,
641
+	.irq_unmask		= irq_chip_unmask_parent,
642
+	.irq_retrigger		= irq_chip_retrigger_hierarchy,
643
+	.irq_set_type		= irq_chip_set_type_parent,
644
+	.irq_set_wake		= stm32_exti_h_set_wake,
645
+	.flags			= IRQCHIP_MASK_ON_SUSPEND,
646
+	.irq_set_affinity	= IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
567647 };
568648 
569649 static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
....@@ -572,24 +652,28 @@
572652 {
573653 	struct stm32_exti_host_data *host_data = dm->host_data;
574654 	struct stm32_exti_chip_data *chip_data;
655
+	const struct stm32_desc_irq *desc;
575656 	struct irq_fwspec *fwspec = data;
576657 	struct irq_fwspec p_fwspec;
577658 	irq_hw_number_t hwirq;
578
-	int p_irq, bank;
659
+	int bank;
579660 
580661 	hwirq = fwspec->param[0];
581662 	bank  = hwirq / IRQS_PER_BANK;
582663 	chip_data = &host_data->chips_data[bank];
583664 
584
-	irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
585
-				      &stm32_exti_h_chip, chip_data);
586665 
587
-	p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
588
-	if (p_irq >= 0) {
666
+	desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
667
+	if (!desc)
668
+		return -EINVAL;
669
+
670
+	irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
671
+				      chip_data);
672
+	if (desc->irq_parent) {
589673 		p_fwspec.fwnode = dm->parent->fwnode;
590674 		p_fwspec.param_count = 3;
591675 		p_fwspec.param[0] = GIC_SPI;
592
-		p_fwspec.param[1] = p_irq;
676
+		p_fwspec.param[1] = desc->irq_parent;
593677 		p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
594678 
595679 		return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
....@@ -641,7 +725,6 @@
641725 	const struct stm32_exti_bank *stm32_bank;
642726 	struct stm32_exti_chip_data *chip_data;
643727 	void __iomem *base = h_data->base;
644
-	u32 irqs_mask;
645728 
646729 	stm32_bank = h_data->drv_data->exti_banks[bank_idx];
647730 	chip_data = &h_data->chips_data[bank_idx];
....@@ -650,10 +733,6 @@
650733 
651734 	raw_spin_lock_init(&chip_data->rlock);
652735 
653
-	/* Determine number of irqs supported */
654
-	writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
655
-	irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
656
-
657736 	/*
658737 	 * This IP has no reset, so after hot reboot we should
659738 	 * clear registers to avoid residue
....@@ -661,8 +740,7 @@
661740 	writel_relaxed(0, base + stm32_bank->imr_ofst);
662741 	writel_relaxed(0, base + stm32_bank->emr_ofst);
663742 
664
-	pr_info("%s: bank%d, External IRQs available:%#x\n",
665
-		node->full_name, bank_idx, irqs_mask);
743
+	pr_info("%pOF: bank%d\n", node, bank_idx);
666744 
667745 	return chip_data;
668746 }
....@@ -683,8 +761,8 @@
683761 	domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
684762 				       &irq_exti_domain_ops, NULL);
685763 	if (!domain) {
686
-		pr_err("%s: Could not register interrupt domain.\n",
687
-		       node->name);
764
+		pr_err("%pOFn: Could not register interrupt domain.\n",
765
+		       node);
688766 		ret = -ENOMEM;
689767 		goto out_unmap;
690768 	}
....@@ -743,52 +821,133 @@
743821 static const struct irq_domain_ops stm32_exti_h_domain_ops = {
744822 	.alloc	= stm32_exti_h_domain_alloc,
745823 	.free	= irq_domain_free_irqs_common,
824
+	.xlate = irq_domain_xlate_twocell,
746825 };
747826 
748
-static int
749
-__init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data,
750
-				 struct device_node *node,
751
-				 struct device_node *parent)
827
+static void stm32_exti_remove_irq(void *data)
752828 {
829
+	struct irq_domain *domain = data;
830
+
831
+	irq_domain_remove(domain);
832
+}
833
+
834
+static int stm32_exti_remove(struct platform_device *pdev)
835
+{
836
+	stm32_exti_h_syscore_deinit();
837
+	return 0;
838
+}
839
+
840
+static int stm32_exti_probe(struct platform_device *pdev)
841
+{
842
+	int ret, i;
843
+	struct device *dev = &pdev->dev;
844
+	struct device_node *np = dev->of_node;
753845 	struct irq_domain *parent_domain, *domain;
754846 	struct stm32_exti_host_data *host_data;
755
-	int ret, i;
847
+	const struct stm32_exti_drv_data *drv_data;
848
+	struct resource *res;
756849 
757
-	parent_domain = irq_find_host(parent);
758
-	if (!parent_domain) {
759
-		pr_err("interrupt-parent not found\n");
760
-		return -EINVAL;
761
-	}
762
-
763
-	host_data = stm32_exti_host_init(drv_data, node);
850
+	host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
764851 	if (!host_data)
765852 		return -ENOMEM;
766853 
854
+	/* check for optional hwspinlock which may be not available yet */
855
+	ret = of_hwspin_lock_get_id(np, 0);
856
+	if (ret == -EPROBE_DEFER)
857
+		/* hwspinlock framework not yet ready */
858
+		return ret;
859
+
860
+	if (ret >= 0) {
861
+		host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
862
+		if (!host_data->hwlock) {
863
+			dev_err(dev, "Failed to request hwspinlock\n");
864
+			return -EINVAL;
865
+		}
866
+	} else if (ret != -ENOENT) {
867
+		/* note: ENOENT is a valid case (means 'no hwspinlock') */
868
+		dev_err(dev, "Failed to get hwspinlock\n");
869
+		return ret;
870
+	}
871
+
872
+	/* initialize host_data */
873
+	drv_data = of_device_get_match_data(dev);
874
+	if (!drv_data) {
875
+		dev_err(dev, "no of match data\n");
876
+		return -ENODEV;
877
+	}
878
+	host_data->drv_data = drv_data;
879
+
880
+	host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
881
+					     sizeof(*host_data->chips_data),
882
+					     GFP_KERNEL);
883
+	if (!host_data->chips_data)
884
+		return -ENOMEM;
885
+
886
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887
+	host_data->base = devm_ioremap_resource(dev, res);
888
+	if (IS_ERR(host_data->base)) {
889
+		dev_err(dev, "Unable to map registers\n");
890
+		return PTR_ERR(host_data->base);
891
+	}
892
+
767893 	for (i = 0; i < drv_data->bank_nr; i++)
768
-		stm32_exti_chip_init(host_data, i, node);
894
+		stm32_exti_chip_init(host_data, i, np);
895
+
896
+	parent_domain = irq_find_host(of_irq_find_parent(np));
897
+	if (!parent_domain) {
898
+		dev_err(dev, "GIC interrupt-parent not found\n");
899
+		return -EINVAL;
900
+	}
769901 
770902 	domain = irq_domain_add_hierarchy(parent_domain, 0,
771903 					  drv_data->bank_nr * IRQS_PER_BANK,
772
-					  node, &stm32_exti_h_domain_ops,
904
+					  np, &stm32_exti_h_domain_ops,
773905 					  host_data);
774906 
775907 	if (!domain) {
776
-		pr_err("%s: Could not register exti domain.\n", node->name);
777
-		ret = -ENOMEM;
778
-		goto out_unmap;
908
+		dev_err(dev, "Could not register exti domain\n");
909
+		return -ENOMEM;
779910 	}
780911 
781
-	stm32_exti_h_syscore_init();
912
+	ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
913
+	if (ret)
914
+		return ret;
915
+
916
+	stm32_exti_h_syscore_init(host_data);
782917 
783918 	return 0;
784
-
785
-out_unmap:
786
-	iounmap(host_data->base);
787
-	kfree(host_data->chips_data);
788
-	kfree(host_data);
789
-	return ret;
790919 }
791920 
921
+/* platform driver only for MP1 */
922
+static const struct of_device_id stm32_exti_ids[] = {
923
+	{ .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
924
+	{},
925
+};
926
+MODULE_DEVICE_TABLE(of, stm32_exti_ids);
927
+
928
+static struct platform_driver stm32_exti_driver = {
929
+	.probe		= stm32_exti_probe,
930
+	.remove		= stm32_exti_remove,
931
+	.driver		= {
932
+		.name	= "stm32_exti",
933
+		.of_match_table = stm32_exti_ids,
934
+	},
935
+};
936
+
937
+static int __init stm32_exti_arch_init(void)
938
+{
939
+	return platform_driver_register(&stm32_exti_driver);
940
+}
941
+
942
+static void __exit stm32_exti_arch_exit(void)
943
+{
944
+	return platform_driver_unregister(&stm32_exti_driver);
945
+}
946
+
947
+arch_initcall(stm32_exti_arch_init);
948
+module_exit(stm32_exti_arch_exit);
949
+
950
+/* no platform driver for F4 and H7 */
792951 static int __init stm32f4_exti_of_init(struct device_node *np,
793952 				       struct device_node *parent)
794953 {
....@@ -804,11 +963,3 @@
804963 }
805964 
806965 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
807
-
808
-static int __init stm32mp1_exti_of_init(struct device_node *np,
809
-					struct device_node *parent)
810
-{
811
-	return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent);
812
-}
813
-
814
-IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init);