write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/irqchip/irq-mips-gic.c
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@@ -48,7 +48,7 @@
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 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
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-static DEFINE_SPINLOCK(gic_lock);
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+static DEFINE_RAW_SPINLOCK(gic_lock);
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 static struct irq_domain *gic_irq_domain;
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 static int gic_shared_intrs;
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 static unsigned int gic_cpu_pin;
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@@ -209,7 +209,7 @@
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 	irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	switch (type & IRQ_TYPE_SENSE_MASK) {
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 	case IRQ_TYPE_EDGE_FALLING:
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 		pol = GIC_POL_FALLING_EDGE;
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@@ -249,7 +249,7 @@
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 	else
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 		irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
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 						 handle_level_irq, NULL);
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return 0;
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 }
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@@ -267,7 +267,7 @@
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 		return -EINVAL;
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 	/* Assumption : cpumask refers to a single CPU */
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	/* Re-route this IRQ */
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 	write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
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@@ -278,7 +278,7 @@
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 		set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
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 	irq_data_update_effective_affinity(d, cpumask_of(cpu));
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return IRQ_SET_MASK_OK;
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 }
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@@ -356,12 +356,12 @@
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 	cd = irq_data_get_irq_chip_data(d);
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 	cd->mask = false;
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_rmask(BIT(intr));
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
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@@ -374,32 +374,43 @@
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 	cd = irq_data_get_irq_chip_data(d);
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 	cd->mask = true;
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_smask(BIT(intr));
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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-static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
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+static void gic_all_vpes_irq_cpu_online(void)
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 {
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-	struct gic_all_vpes_chip_data *cd;
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-	unsigned int intr;
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+	static const unsigned int local_intrs[] = {
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+		GIC_LOCAL_INT_TIMER,
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+		GIC_LOCAL_INT_PERFCTR,
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+		GIC_LOCAL_INT_FDC,
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+	};
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+	unsigned long flags;
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+	int i;
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-	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
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-	cd = irq_data_get_irq_chip_data(d);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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-	write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
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-	if (cd->mask)
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-		write_gic_vl_smask(BIT(intr));
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+	for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
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+		unsigned int intr = local_intrs[i];
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+		struct gic_all_vpes_chip_data *cd;
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+
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+		cd = &gic_all_vpes_chip_data[intr];
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+		write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
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+		if (cd->mask)
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+			write_gic_vl_smask(BIT(intr));
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+	}
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+
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 }
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 static struct irq_chip gic_all_vpes_local_irq_controller = {
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 	.name			= "MIPS GIC Local",
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 	.irq_mask		= gic_mask_local_irq_all_vpes,
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 	.irq_unmask		= gic_unmask_local_irq_all_vpes,
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-	.irq_cpu_online		= gic_all_vpes_irq_cpu_online,
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 };
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 static void __gic_irq_dispatch(void)
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@@ -423,11 +434,11 @@
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 	data = irq_get_irq_data(virq);
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
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 	write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
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 	irq_data_update_effective_affinity(data, cpumask_of(cpu));
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return 0;
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 }
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@@ -480,6 +491,10 @@
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 	intr = GIC_HWIRQ_TO_LOCAL(hwirq);
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 	map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
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+	/*
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+	 * If adding support for more per-cpu interrupts, keep the the
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+	 * array in gic_all_vpes_irq_cpu_online() in sync.
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+	 */
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 	switch (intr) {
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 	case GIC_LOCAL_INT_TIMER:
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 		/* CONFIG_MIPS_CMP workaround (see __gic_init) */
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@@ -518,12 +533,12 @@
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 	if (!gic_local_irq_is_routable(intr))
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 		return -EPERM;
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-	spin_lock_irqsave(&gic_lock, flags);
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+	raw_spin_lock_irqsave(&gic_lock, flags);
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 	for_each_online_cpu(cpu) {
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 		write_gic_vl_other(mips_cm_vp_id(cpu));
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 		write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
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 	}
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-	spin_unlock_irqrestore(&gic_lock, flags);
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+	raw_spin_unlock_irqrestore(&gic_lock, flags);
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 	return 0;
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 }
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@@ -710,8 +725,8 @@
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 	/* Clear all local IRQ masks (ie. disable all local interrupts) */
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 	write_gic_vl_rmask(~0);
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-	/* Invoke irq_cpu_online callbacks to enable desired interrupts */
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-	irq_cpu_online();
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+	/* Enable desired interrupts */
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+	gic_all_vpes_irq_cpu_online();
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 	return 0;
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 }