write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/hwtracing/intel_th/msu.h
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@@ -1,4 +1,4 @@
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-// SPDX-License-Identifier: GPL-2.0
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+/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures
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  *
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@@ -11,6 +11,7 @@
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 enum {
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 	REG_MSU_MSUPARAMS	= 0x0000,
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 	REG_MSU_MSUSTS		= 0x0008,
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+	REG_MSU_MINTCTL		= 0x0004, /* MSU-global interrupt control */
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 	REG_MSU_MSC0CTL		= 0x0100, /* MSC0 control */
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 	REG_MSU_MSC0STS		= 0x0104, /* MSC0 status */
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 	REG_MSU_MSC0BAR		= 0x0108, /* MSC0 output base address */
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@@ -28,6 +29,8 @@
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 /* MSUSTS bits */
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 #define MSUSTS_MSU_INT	BIT(0)
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+#define MSUSTS_MSC0BLAST	BIT(16)
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+#define MSUSTS_MSC1BLAST	BIT(24)
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 /* MSCnCTL bits */
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 #define MSC_EN		BIT(0)
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@@ -36,13 +39,10 @@
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 #define MSC_MODE	(BIT(4) | BIT(5))
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 #define MSC_LEN		(BIT(8) | BIT(9) | BIT(10))
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-/* MSC operating modes (MSC_MODE) */
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-enum {
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-	MSC_MODE_SINGLE	= 0,
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-	MSC_MODE_MULTI,
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-	MSC_MODE_EXI,
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-	MSC_MODE_DEBUG,
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-};
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+/* MINTCTL bits */
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+#define MICDE		BIT(0)
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+#define M0BLIE		BIT(16)
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+#define M1BLIE		BIT(24)
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 /* MSCnSTS bits */
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 #define MSCSTS_WRAPSTAT	BIT(1)	/* Wrap occurred */
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@@ -85,9 +85,19 @@
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 	return bdesc->valid_dw * 4 - MSC_BDESC;
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 }
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+static inline unsigned long msc_total_sz(struct msc_block_desc *bdesc)
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+{
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+	return bdesc->valid_dw * 4;
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+}
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+
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+static inline unsigned long msc_block_sz(struct msc_block_desc *bdesc)
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+{
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+	return bdesc->block_sz * 64 - MSC_BDESC;
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+}
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+
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 static inline bool msc_block_wrapped(struct msc_block_desc *bdesc)
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 {
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-	if (bdesc->hw_tag & MSC_HW_TAG_BLOCKWRAP)
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+	if (bdesc->hw_tag & (MSC_HW_TAG_BLOCKWRAP | MSC_HW_TAG_WINWRAP))
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 		return true;
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 	return false;
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@@ -96,7 +106,7 @@
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 static inline bool msc_block_last_written(struct msc_block_desc *bdesc)
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 {
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 	if ((bdesc->hw_tag & MSC_HW_TAG_ENDBIT) ||
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-	    (msc_data_sz(bdesc) != DATA_IN_PAGE))
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+	    (msc_data_sz(bdesc) != msc_block_sz(bdesc)))
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 		return true;
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 	return false;