write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/hwtracing/intel_th/gth.c
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@@ -308,6 +308,11 @@
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 	iowrite32(0, gth->base + REG_GTH_SCR);
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 	iowrite32(0xfc, gth->base + REG_GTH_SCR2);
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+	/* setup CTS for single trigger */
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+	iowrite32(CTS_EVENT_ENABLE_IF_ANYTHING, gth->base + REG_CTS_C0S0_EN);
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+	iowrite32(CTS_ACTION_CONTROL_SET_STATE(CTS_STATE_IDLE) |
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+		  CTS_ACTION_CONTROL_TRIGGER, gth->base + REG_CTS_C0S0_ACT);
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+
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 	return 0;
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 }
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@@ -457,6 +462,68 @@
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 }
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 /**
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+ * intel_th_gth_stop() - stop tracing to an output device
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+ * @gth:		GTH device
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+ * @output:		output device's descriptor
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+ * @capture_done:	set when no more traces will be captured
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+ *
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+ * This will stop tracing using force storeEn off signal and wait for the
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+ * pipelines to be empty for the corresponding output port.
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+ */
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+static void intel_th_gth_stop(struct gth_device *gth,
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+			      struct intel_th_output *output,
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+			      bool capture_done)
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+{
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+	struct intel_th_device *outdev =
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+		container_of(output, struct intel_th_device, output);
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+	struct intel_th_driver *outdrv =
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+		to_intel_th_driver(outdev->dev.driver);
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+	unsigned long count;
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+	u32 reg;
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+	u32 scr2 = 0xfc | (capture_done ? 1 : 0);
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+
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+	iowrite32(0, gth->base + REG_GTH_SCR);
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+	iowrite32(scr2, gth->base + REG_GTH_SCR2);
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+
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+	/* wait on pipeline empty for the given port */
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+	for (reg = 0, count = GTH_PLE_WAITLOOP_DEPTH;
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+	     count && !(reg & BIT(output->port)); count--) {
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+		reg = ioread32(gth->base + REG_GTH_STAT);
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+		cpu_relax();
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+	}
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+
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+	if (!count)
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+		dev_dbg(gth->dev, "timeout waiting for GTH[%d] PLE\n",
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+			output->port);
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+
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+	/* wait on output piepline empty */
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+	if (outdrv->wait_empty)
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+		outdrv->wait_empty(outdev);
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+
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+	/* clear force capture done for next captures */
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+	iowrite32(0xfc, gth->base + REG_GTH_SCR2);
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+}
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+
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+/**
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+ * intel_th_gth_start() - start tracing to an output device
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+ * @gth:	GTH device
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+ * @output:	output device's descriptor
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+ *
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+ * This will start tracing using force storeEn signal.
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+ */
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+static void intel_th_gth_start(struct gth_device *gth,
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+			       struct intel_th_output *output)
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+{
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+	u32 scr = 0xfc0000;
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+
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+	if (output->multiblock)
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+		scr |= 0xff;
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+
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+	iowrite32(scr, gth->base + REG_GTH_SCR);
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+	iowrite32(0, gth->base + REG_GTH_SCR2);
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+}
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+
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+/**
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  * intel_th_gth_disable() - disable tracing to an output device
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  * @thdev:	GTH device
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  * @output:	output device's descriptor
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@@ -469,7 +536,6 @@
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 				 struct intel_th_output *output)
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 {
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 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
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-	unsigned long count;
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 	int master;
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 	u32 reg;
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541
 
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@@ -482,22 +548,7 @@
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 	}
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 	spin_unlock(&gth->gth_lock);
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-	iowrite32(0, gth->base + REG_GTH_SCR);
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-	iowrite32(0xfd, gth->base + REG_GTH_SCR2);
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-
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-	/* wait on pipeline empty for the given port */
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-	for (reg = 0, count = GTH_PLE_WAITLOOP_DEPTH;
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-	     count && !(reg & BIT(output->port)); count--) {
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-		reg = ioread32(gth->base + REG_GTH_STAT);
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-		cpu_relax();
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-	}
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-
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-	/* clear force capture done for next captures */
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-	iowrite32(0xfc, gth->base + REG_GTH_SCR2);
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-
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-	if (!count)
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-		dev_dbg(&thdev->dev, "timeout waiting for GTH[%d] PLE\n",
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-			output->port);
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+	intel_th_gth_stop(gth, output, true);
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 	reg = ioread32(gth->base + REG_GTH_SCRPD0);
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 	reg &= ~output->scratchpad;
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@@ -541,17 +592,14 @@
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 {
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 	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
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 	struct intel_th *th = to_intel_th(thdev);
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-	u32 scr = 0xfc0000, scrpd;
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 	int master;
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+	u32 scrpd;
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 	spin_lock(&gth->gth_lock);
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 	for_each_set_bit(master, gth->output[output->port].master,
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 			 TH_CONFIGURABLE_MASTERS + 1) {
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 		gth_master_set(gth, master, output->port);
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 	}
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-
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-	if (output->multiblock)
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-		scr |= 0xff;
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 	output->active = true;
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 	spin_unlock(&gth->gth_lock);
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@@ -563,8 +611,41 @@
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 	scrpd |= output->scratchpad;
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 	iowrite32(scrpd, gth->base + REG_GTH_SCRPD0);
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-	iowrite32(scr, gth->base + REG_GTH_SCR);
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-	iowrite32(0, gth->base + REG_GTH_SCR2);
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+	intel_th_gth_start(gth, output);
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+}
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+
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+/**
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+ * intel_th_gth_switch() - execute a switch sequence
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+ * @thdev:	GTH device
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+ * @output:	output device's descriptor
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+ *
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+ * This will execute a switch sequence that will trigger a switch window
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+ * when tracing to MSC in multi-block mode.
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+ */
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+static void intel_th_gth_switch(struct intel_th_device *thdev,
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+				struct intel_th_output *output)
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+{
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+	struct gth_device *gth = dev_get_drvdata(&thdev->dev);
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+	unsigned long count;
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+	u32 reg;
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+
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+	/* trigger */
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+	iowrite32(0, gth->base + REG_CTS_CTL);
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+	iowrite32(CTS_CTL_SEQUENCER_ENABLE, gth->base + REG_CTS_CTL);
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+	/* wait on trigger status */
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+	for (reg = 0, count = CTS_TRIG_WAITLOOP_DEPTH;
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+	     count && !(reg & BIT(4)); count--) {
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+		reg = ioread32(gth->base + REG_CTS_STAT);
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+		cpu_relax();
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+	}
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+	if (!count)
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+		dev_dbg(&thdev->dev, "timeout waiting for CTS Trigger\n");
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+
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+	/* De-assert the trigger */
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+	iowrite32(0, gth->base + REG_CTS_CTL);
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+
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+	intel_th_gth_stop(gth, output, false);
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+	intel_th_gth_start(gth, output);
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 }
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 /**
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@@ -751,6 +832,7 @@
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 	.set_output	= intel_th_gth_set_output,
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 	.prepare	= intel_th_gth_prepare,
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 	.enable		= intel_th_gth_enable,
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+	.trig_switch	= intel_th_gth_switch,
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 	.disable	= intel_th_gth_disable,
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 	.driver	= {
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 		.name	= "gth",