write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
..
..
@@ -3,15 +3,14 @@
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3
  * Copyright (C) 2014-2018 Etnaviv Project
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4
  */
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5
 
6
+#include <linux/bitops.h>
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+#include <linux/dma-mapping.h>
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8
 #include <linux/platform_device.h>
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9
 #include <linux/sizes.h>
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 #include <linux/slab.h>
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-#include <linux/dma-mapping.h>
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-#include <linux/bitops.h>
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11
 
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 #include "etnaviv_gpu.h"
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 #include "etnaviv_mmu.h"
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-#include "etnaviv_iommu.h"
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 #include "state_hi.xml.h"
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15
 
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 #define PT_SIZE		SZ_2M
..
..
@@ -19,124 +18,93 @@
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18
 
20
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 #define GPU_MEM_START	0x80000000
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20
 
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-struct etnaviv_iommuv1_domain {
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-	struct etnaviv_iommu_domain base;
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+struct etnaviv_iommuv1_context {
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+	struct etnaviv_iommu_context base;
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 	u32 *pgtable_cpu;
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 	dma_addr_t pgtable_dma;
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 };
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26
 
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-static struct etnaviv_iommuv1_domain *
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-to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
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+static struct etnaviv_iommuv1_context *
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+to_v1_context(struct etnaviv_iommu_context *context)
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 {
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-	return container_of(domain, struct etnaviv_iommuv1_domain, base);
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+	return container_of(context, struct etnaviv_iommuv1_context, base);
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 }
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32
 
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-static int __etnaviv_iommu_init(struct etnaviv_iommuv1_domain *etnaviv_domain)
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+static void etnaviv_iommuv1_free(struct etnaviv_iommu_context *context)
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 {
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-	u32 *p;
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-	int i;
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+	struct etnaviv_iommuv1_context *v1_context = to_v1_context(context);
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36
 
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-	etnaviv_domain->base.bad_page_cpu =
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-			dma_alloc_wc(etnaviv_domain->base.dev, SZ_4K,
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-				     &etnaviv_domain->base.bad_page_dma,
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-				     GFP_KERNEL);
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-	if (!etnaviv_domain->base.bad_page_cpu)
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-		return -ENOMEM;
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+	drm_mm_takedown(&context->mm);
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38
 
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-	p = etnaviv_domain->base.bad_page_cpu;
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-	for (i = 0; i < SZ_4K / 4; i++)
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-		*p++ = 0xdead55aa;
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+	dma_free_wc(context->global->dev, PT_SIZE, v1_context->pgtable_cpu,
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+		    v1_context->pgtable_dma);
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-	etnaviv_domain->pgtable_cpu = dma_alloc_wc(etnaviv_domain->base.dev,
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-						   PT_SIZE,
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-						   &etnaviv_domain->pgtable_dma,
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-						   GFP_KERNEL);
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-	if (!etnaviv_domain->pgtable_cpu) {
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-		dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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-			    etnaviv_domain->base.bad_page_cpu,
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-			    etnaviv_domain->base.bad_page_dma);
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-		return -ENOMEM;
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-	}
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+	context->global->v1.shared_context = NULL;
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43
 
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-	memset32(etnaviv_domain->pgtable_cpu, etnaviv_domain->base.bad_page_dma,
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-		 PT_ENTRIES);
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-
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-	return 0;
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+	kfree(v1_context);
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 }
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46
 
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-static void etnaviv_iommuv1_domain_free(struct etnaviv_iommu_domain *domain)
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-{
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-	struct etnaviv_iommuv1_domain *etnaviv_domain =
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-			to_etnaviv_domain(domain);
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-
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-	dma_free_wc(etnaviv_domain->base.dev, PT_SIZE,
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-		    etnaviv_domain->pgtable_cpu, etnaviv_domain->pgtable_dma);
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-
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-	dma_free_wc(etnaviv_domain->base.dev, SZ_4K,
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-		    etnaviv_domain->base.bad_page_cpu,
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-		    etnaviv_domain->base.bad_page_dma);
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-
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-	kfree(etnaviv_domain);
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-}
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-
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-static int etnaviv_iommuv1_map(struct etnaviv_iommu_domain *domain,
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+static int etnaviv_iommuv1_map(struct etnaviv_iommu_context *context,
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 			       unsigned long iova, phys_addr_t paddr,
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 			       size_t size, int prot)
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 {
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-	struct etnaviv_iommuv1_domain *etnaviv_domain = to_etnaviv_domain(domain);
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+	struct etnaviv_iommuv1_context *v1_context = to_v1_context(context);
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 	unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
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53
 
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 	if (size != SZ_4K)
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 		return -EINVAL;
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56
 
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-	etnaviv_domain->pgtable_cpu[index] = paddr;
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+	v1_context->pgtable_cpu[index] = paddr;
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58
 
94
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 	return 0;
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60
 }
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61
 
97
-static size_t etnaviv_iommuv1_unmap(struct etnaviv_iommu_domain *domain,
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+static size_t etnaviv_iommuv1_unmap(struct etnaviv_iommu_context *context,
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 	unsigned long iova, size_t size)
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64
 {
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-	struct etnaviv_iommuv1_domain *etnaviv_domain =
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-			to_etnaviv_domain(domain);
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+	struct etnaviv_iommuv1_context *v1_context = to_v1_context(context);
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 	unsigned int index = (iova - GPU_MEM_START) / SZ_4K;
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67
 
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 	if (size != SZ_4K)
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 		return -EINVAL;
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70
 
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-	etnaviv_domain->pgtable_cpu[index] = etnaviv_domain->base.bad_page_dma;
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+	v1_context->pgtable_cpu[index] = context->global->bad_page_dma;
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72
 
109
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 	return SZ_4K;
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74
 }
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75
 
112
-static size_t etnaviv_iommuv1_dump_size(struct etnaviv_iommu_domain *domain)
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+static size_t etnaviv_iommuv1_dump_size(struct etnaviv_iommu_context *context)
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 {
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78
 	return PT_SIZE;
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79
 }
116
80
 
117
-static void etnaviv_iommuv1_dump(struct etnaviv_iommu_domain *domain, void *buf)
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+static void etnaviv_iommuv1_dump(struct etnaviv_iommu_context *context,
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+				 void *buf)
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 {
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-	struct etnaviv_iommuv1_domain *etnaviv_domain =
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-			to_etnaviv_domain(domain);
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+	struct etnaviv_iommuv1_context *v1_context = to_v1_context(context);
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85
 
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-	memcpy(buf, etnaviv_domain->pgtable_cpu, PT_SIZE);
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+	memcpy(buf, v1_context->pgtable_cpu, PT_SIZE);
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87
 }
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88
 
125
-void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
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+static void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu,
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+			     struct etnaviv_iommu_context *context)
126
91
 {
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-	struct etnaviv_iommuv1_domain *etnaviv_domain =
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-			to_etnaviv_domain(gpu->mmu->domain);
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+	struct etnaviv_iommuv1_context *v1_context = to_v1_context(context);
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93
 	u32 pgtable;
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94
 
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+	if (gpu->mmu_context)
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+		etnaviv_iommu_context_put(gpu->mmu_context);
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+	gpu->mmu_context = etnaviv_iommu_context_get(context);
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+
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 	/* set base addresses */
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-	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
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-	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
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-	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
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-	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
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-	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
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+	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base);
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+	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base);
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+	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base);
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+	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base);
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+	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base);
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105
 
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 	/* set page table address in MC */
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-	pgtable = (u32)etnaviv_domain->pgtable_dma;
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+	pgtable = (u32)v1_context->pgtable_dma;
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108
 
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 	gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable);
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110
 	gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable);
..
..
@@ -145,39 +113,64 @@
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113
 	gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable);
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114
 }
147
115
 
148
-static const struct etnaviv_iommu_domain_ops etnaviv_iommuv1_ops = {
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-	.free = etnaviv_iommuv1_domain_free,
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+
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+const struct etnaviv_iommu_ops etnaviv_iommuv1_ops = {
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+	.free = etnaviv_iommuv1_free,
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 	.map = etnaviv_iommuv1_map,
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 	.unmap = etnaviv_iommuv1_unmap,
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 	.dump_size = etnaviv_iommuv1_dump_size,
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 	.dump = etnaviv_iommuv1_dump,
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+	.restore = etnaviv_iommuv1_restore,
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 };
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125
 
156
-struct etnaviv_iommu_domain *
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-etnaviv_iommuv1_domain_alloc(struct etnaviv_gpu *gpu)
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+struct etnaviv_iommu_context *
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+etnaviv_iommuv1_context_alloc(struct etnaviv_iommu_global *global)
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128
 {
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-	struct etnaviv_iommuv1_domain *etnaviv_domain;
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-	struct etnaviv_iommu_domain *domain;
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-	int ret;
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+	struct etnaviv_iommuv1_context *v1_context;
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+	struct etnaviv_iommu_context *context;
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131
 
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-	etnaviv_domain = kzalloc(sizeof(*etnaviv_domain), GFP_KERNEL);
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-	if (!etnaviv_domain)
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+	mutex_lock(&global->lock);
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+
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+	/*
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+	 * MMUv1 does not support switching between different contexts without
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+	 * a stop the world operation, so we only support a single shared
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+	 * context with this version.
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+	 */
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+	if (global->v1.shared_context) {
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+		context = global->v1.shared_context;
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+		etnaviv_iommu_context_get(context);
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+		mutex_unlock(&global->lock);
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+		return context;
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+	}
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+
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+	v1_context = kzalloc(sizeof(*v1_context), GFP_KERNEL);
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+	if (!v1_context) {
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+		mutex_unlock(&global->lock);
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149
 		return NULL;
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+	}
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151
 
167
-	domain = &etnaviv_domain->base;
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-
169
-	domain->dev = gpu->dev;
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-	domain->base = GPU_MEM_START;
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-	domain->size = PT_ENTRIES * SZ_4K;
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-	domain->ops = &etnaviv_iommuv1_ops;
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-
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-	ret = __etnaviv_iommu_init(etnaviv_domain);
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-	if (ret)
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+	v1_context->pgtable_cpu = dma_alloc_wc(global->dev, PT_SIZE,
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+					       &v1_context->pgtable_dma,
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+					       GFP_KERNEL);
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+	if (!v1_context->pgtable_cpu)
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156
 		goto out_free;
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157
 
178
-	return &etnaviv_domain->base;
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+	memset32(v1_context->pgtable_cpu, global->bad_page_dma, PT_ENTRIES);
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+
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+	context = &v1_context->base;
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+	context->global = global;
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+	kref_init(&context->refcount);
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+	mutex_init(&context->lock);
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+	INIT_LIST_HEAD(&context->mappings);
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+	drm_mm_init(&context->mm, GPU_MEM_START, PT_ENTRIES * SZ_4K);
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+	context->global->v1.shared_context = context;
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+
168
+	mutex_unlock(&global->lock);
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+
170
+	return context;
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171
 
180
172
 out_free:
181
-	kfree(etnaviv_domain);
173
+	mutex_unlock(&global->lock);
174
+	kfree(v1_context);
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175
 	return NULL;
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176
 }