forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
....@@ -3,6 +3,8 @@
33  * Copyright (C) 2014-2018 Etnaviv Project
44  */
55 
6
+#include <drm/drm_drv.h>
7
+
68 #include "etnaviv_cmdbuf.h"
79 #include "etnaviv_gpu.h"
810 #include "etnaviv_gem.h"
....@@ -10,6 +12,7 @@
1012 
1113 #include "common.xml.h"
1214 #include "state.xml.h"
15
+#include "state_blt.xml.h"
1316 #include "state_hi.xml.h"
1417 #include "state_3d.xml.h"
1518 #include "cmdstream.xml.h"
....@@ -116,7 +119,9 @@
116119 	u32 *ptr = buf->vaddr + off;
117120 
118121 	dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
119
-			ptr, etnaviv_cmdbuf_get_va(buf) + off, size - len * 4 - off);
122
+			ptr, etnaviv_cmdbuf_get_va(buf,
123
+			&gpu->mmu_context->cmdbuf_mapping) +
124
+			off, size - len * 4 - off);
120125 
121126 	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
122127 			ptr, len * 4, 0);
....@@ -149,7 +154,9 @@
149154 	if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
150155 		buffer->user_size = 0;
151156 
152
-	return etnaviv_cmdbuf_get_va(buffer) + buffer->user_size;
157
+	return etnaviv_cmdbuf_get_va(buffer,
158
+				     &gpu->mmu_context->cmdbuf_mapping) +
159
+	       buffer->user_size;
153160 }
154161 
155162 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
....@@ -162,8 +169,9 @@
162169 	buffer->user_size = 0;
163170 
164171 	CMD_WAIT(buffer);
165
-	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +
166
-		 buffer->user_size - 4);
172
+	CMD_LINK(buffer, 2,
173
+		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
174
+		 + buffer->user_size - 4);
167175 
168176 	return buffer->user_size / 8;
169177 }
....@@ -203,7 +211,7 @@
203211 	return buffer->user_size / 8;
204212 }
205213 
206
-u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu)
214
+u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)
207215 {
208216 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
209217 
....@@ -212,7 +220,7 @@
212220 	buffer->user_size = 0;
213221 
214222 	CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,
215
-		       VIVS_MMUv2_PTA_CONFIG_INDEX(0));
223
+		       VIVS_MMUv2_PTA_CONFIG_INDEX(id));
216224 
217225 	CMD_END(buffer);
218226 
....@@ -226,6 +234,8 @@
226234 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
227235 	unsigned int waitlink_offset = buffer->user_size - 16;
228236 	u32 link_target, flush = 0;
237
+	bool has_blt = !!(gpu->identity.minor_features5 &
238
+			  chipMinorFeatures5_BLT_ENGINE);
229239 
230240 	lockdep_assert_held(&gpu->lock);
231241 
....@@ -241,16 +251,38 @@
241251 	if (flush) {
242252 		unsigned int dwords = 7;
243253 
254
+		if (has_blt)
255
+			dwords += 10;
256
+
244257 		link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);
245258 
246259 		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
247260 		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
261
+		if (has_blt) {
262
+			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
263
+			CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
264
+			CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
265
+			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
266
+		}
248267 		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
249
-		if (gpu->exec_state == ETNA_PIPE_3D)
250
-			CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
251
-				       VIVS_TS_FLUSH_CACHE_FLUSH);
268
+		if (gpu->exec_state == ETNA_PIPE_3D) {
269
+			if (has_blt) {
270
+				CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
271
+				CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
272
+				CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
273
+			} else {
274
+				CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
275
+					       VIVS_TS_FLUSH_CACHE_FLUSH);
276
+			}
277
+		}
252278 		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
253279 		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
280
+		if (has_blt) {
281
+			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
282
+			CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
283
+			CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
284
+			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
285
+		}
254286 		CMD_END(buffer);
255287 
256288 		etnaviv_buffer_replace_wait(buffer, waitlink_offset,
....@@ -289,8 +321,9 @@
289321 
290322 	/* Append waitlink */
291323 	CMD_WAIT(buffer);
292
-	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +
293
-			    buffer->user_size - 4);
324
+	CMD_LINK(buffer, 2,
325
+		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
326
+		 + buffer->user_size - 4);
294327 
295328 	/*
296329 	 * Kick off the 'sync point' command by replacing the previous
....@@ -304,26 +337,31 @@
304337 
305338 /* Append a command buffer to the ring buffer. */
306339 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
307
-	unsigned int event, struct etnaviv_cmdbuf *cmdbuf)
340
+	struct etnaviv_iommu_context *mmu_context, unsigned int event,
341
+	struct etnaviv_cmdbuf *cmdbuf)
308342 {
309343 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
310344 	unsigned int waitlink_offset = buffer->user_size - 16;
311345 	u32 return_target, return_dwords;
312346 	u32 link_target, link_dwords;
313347 	bool switch_context = gpu->exec_state != exec_state;
314
-	unsigned int new_flush_seq = READ_ONCE(gpu->mmu->flush_seq);
315
-	bool need_flush = gpu->flush_seq != new_flush_seq;
348
+	bool switch_mmu_context = gpu->mmu_context != mmu_context;
349
+	unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
350
+	bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;
351
+	bool has_blt = !!(gpu->identity.minor_features5 &
352
+			  chipMinorFeatures5_BLT_ENGINE);
316353 
317354 	lockdep_assert_held(&gpu->lock);
318355 
319
-	if (drm_debug & DRM_UT_DRIVER)
356
+	if (drm_debug_enabled(DRM_UT_DRIVER))
320357 		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
321358 
322
-	link_target = etnaviv_cmdbuf_get_va(cmdbuf);
359
+	link_target = etnaviv_cmdbuf_get_va(cmdbuf,
360
+					    &gpu->mmu_context->cmdbuf_mapping);
323361 	link_dwords = cmdbuf->size / 8;
324362 
325363 	/*
326
-	 * If we need maintanence prior to submitting this buffer, we will
364
+	 * If we need maintenance prior to submitting this buffer, we will
327365 	 * need to append a mmu flush load state, followed by a new
328366 	 * link to this buffer - a total of four additional words.
329367 	 */
....@@ -335,7 +373,7 @@
335373 
336374 		/* flush command */
337375 		if (need_flush) {
338
-			if (gpu->mmu->version == ETNAVIV_IOMMU_V1)
376
+			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)
339377 				extra_dwords += 1;
340378 			else
341379 				extra_dwords += 3;
....@@ -345,11 +383,27 @@
345383 		if (switch_context)
346384 			extra_dwords += 4;
347385 
386
+		/* PTA load command */
387
+		if (switch_mmu_context && gpu->sec_mode == ETNA_SEC_KERNEL)
388
+			extra_dwords += 1;
389
+
348390 		target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
391
+		/*
392
+		 * Switch MMU context if necessary. Must be done after the
393
+		 * link target has been calculated, as the jump forward in the
394
+		 * kernel ring still uses the last active MMU context before
395
+		 * the switch.
396
+		 */
397
+		if (switch_mmu_context) {
398
+			struct etnaviv_iommu_context *old_context = gpu->mmu_context;
399
+
400
+			gpu->mmu_context = etnaviv_iommu_context_get(mmu_context);
401
+			etnaviv_iommu_context_put(old_context);
402
+		}
349403 
350404 		if (need_flush) {
351405 			/* Add the MMU flush */
352
-			if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {
406
+			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {
353407 				CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
354408 					       VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
355409 					       VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
....@@ -357,10 +411,23 @@
357411 					       VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
358412 					       VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
359413 			} else {
414
+				u32 flush = VIVS_MMUv2_CONFIGURATION_MODE_MASK |
415
+					    VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH;
416
+
417
+				if (switch_mmu_context &&
418
+				    gpu->sec_mode == ETNA_SEC_KERNEL) {
419
+					unsigned short id =
420
+						etnaviv_iommuv2_get_pta_id(gpu->mmu_context);
421
+					CMD_LOAD_STATE(buffer,
422
+						VIVS_MMUv2_PTA_CONFIG,
423
+						VIVS_MMUv2_PTA_CONFIG_INDEX(id));
424
+				}
425
+
426
+				if (gpu->sec_mode == ETNA_SEC_NONE)
427
+					flush |= etnaviv_iommuv2_get_mtlb_addr(gpu->mmu_context);
428
+
360429 				CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
361
-					VIVS_MMUv2_CONFIGURATION_MODE_MASK |
362
-					VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK |
363
-					VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH);
430
+					       flush);
364431 				CMD_SEM(buffer, SYNC_RECIPIENT_FE,
365432 					SYNC_RECIPIENT_PE);
366433 				CMD_STALL(buffer, SYNC_RECIPIENT_FE,
....@@ -376,6 +443,8 @@
376443 		}
377444 
378445 		/* And the link to the submitted buffer */
446
+		link_target = etnaviv_cmdbuf_get_va(cmdbuf,
447
+					&gpu->mmu_context->cmdbuf_mapping);
379448 		CMD_LINK(buffer, link_dwords, link_target);
380449 
381450 		/* Update the link target to point to above instructions */
....@@ -390,6 +459,15 @@
390459 	 * 2 semaphore stall + 1 event + 1 wait + 1 link.
391460 	 */
392461 	return_dwords = 7;
462
+
463
+	/*
464
+	 * When the BLT engine is present we need 6 more dwords in the return
465
+	 * target: 3 enable/flush/disable + 4 enable/semaphore stall/disable,
466
+	 * but we don't need the normal TS flush state.
467
+	 */
468
+	if (has_blt)
469
+		return_dwords += 6;
470
+
393471 	return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
394472 	CMD_LINK(cmdbuf, return_dwords, return_target);
395473 
....@@ -404,23 +482,39 @@
404482 		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
405483 				       VIVS_GL_FLUSH_CACHE_DEPTH |
406484 				       VIVS_GL_FLUSH_CACHE_COLOR);
407
-		CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
408
-				       VIVS_TS_FLUSH_CACHE_FLUSH);
485
+		if (has_blt) {
486
+			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
487
+			CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
488
+			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
489
+		} else {
490
+			CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
491
+					       VIVS_TS_FLUSH_CACHE_FLUSH);
492
+		}
409493 	}
410494 	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
411495 	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
496
+
497
+	if (has_blt) {
498
+		CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
499
+		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
500
+		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
501
+		CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
502
+	}
503
+
412504 	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
413505 		       VIVS_GL_EVENT_FROM_PE);
414506 	CMD_WAIT(buffer);
415
-	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer) +
416
-			    buffer->user_size - 4);
507
+	CMD_LINK(buffer, 2,
508
+		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
509
+		 + buffer->user_size - 4);
417510 
418
-	if (drm_debug & DRM_UT_DRIVER)
511
+	if (drm_debug_enabled(DRM_UT_DRIVER))
419512 		pr_info("stream link to 0x%08x @ 0x%08x %p\n",
420
-			return_target, etnaviv_cmdbuf_get_va(cmdbuf),
513
+			return_target,
514
+			etnaviv_cmdbuf_get_va(cmdbuf, &gpu->mmu_context->cmdbuf_mapping),
421515 			cmdbuf->vaddr);
422516 
423
-	if (drm_debug & DRM_UT_DRIVER) {
517
+	if (drm_debug_enabled(DRM_UT_DRIVER)) {
424518 		print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
425519 			       cmdbuf->vaddr, cmdbuf->size, 0);
426520 
....@@ -439,8 +533,6 @@
439533 				    VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
440534 				    link_target);
441535 
442
-	if (drm_debug & DRM_UT_DRIVER)
536
+	if (drm_debug_enabled(DRM_UT_DRIVER))
443537 		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
444
-
445
-	gpu->lastctx = cmdbuf->ctx;
446538 }