forked from ~ljy/RK356X_SDK_RELEASE
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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/drivers/gpio/gpio-stp-xway.c
....@@ -1,10 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
2
- *  This program is free software; you can redistribute it and/or modify it
3
- *  under the terms of the GNU General Public License version 2 as published
4
- *  by the Free Software Foundation.
53  *
64  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
7
- *
85  */
96 
107 #include <linux/slab.h>
....@@ -17,8 +14,6 @@
1714 #include <linux/io.h>
1815 #include <linux/clk.h>
1916 #include <linux/err.h>
20
-
21
-#include <lantiq_soc.h>
2217 
2318 /*
2419  * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
....@@ -46,7 +41,10 @@
4641 #define XWAY_STP_4HZ		BIT(23)
4742 #define XWAY_STP_8HZ		BIT(24)
4843 #define XWAY_STP_10HZ		(BIT(24) | BIT(23))
49
-#define XWAY_STP_SPEED_MASK	(0xf << 23)
44
+#define XWAY_STP_SPEED_MASK	(BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
45
+
46
+#define XWAY_STP_FPIS_VALUE	BIT(21)
47
+#define XWAY_STP_FPIS_MASK	(BIT(20) | BIT(21))
5048 
5149 /* clock source for automatic update */
5250 #define XWAY_STP_UPD_FPI	BIT(31)
....@@ -59,7 +57,9 @@
5957 /* 2 groups of 3 bits can be driven by the phys */
6058 #define XWAY_STP_PHY_MASK	0x7
6159 #define XWAY_STP_PHY1_SHIFT	27
62
-#define XWAY_STP_PHY2_SHIFT	15
60
+#define XWAY_STP_PHY2_SHIFT	3
61
+#define XWAY_STP_PHY3_SHIFT	6
62
+#define XWAY_STP_PHY4_SHIFT	15
6363 
6464 /* STP has 3 groups of 8 bits */
6565 #define XWAY_STP_GROUP0		BIT(0)
....@@ -74,8 +74,7 @@
7474 #define xway_stp_r32(m, reg)		__raw_readl(m + reg)
7575 #define xway_stp_w32(m, val, reg)	__raw_writel(val, m + reg)
7676 #define xway_stp_w32_mask(m, clear, set, reg) \
77
-		ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \
78
-		m + reg)
77
+		xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)
7978 
8079 struct xway_stp {
8180 	struct gpio_chip gc;
....@@ -86,6 +85,8 @@
8685 	u8 dsl;		/* the 2 LSBs can be driven by the dsl core */
8786 	u8 phy1;	/* 3 bits can be driven by phy1 */
8887 	u8 phy2;	/* 3 bits can be driven by phy2 */
88
+	u8 phy3;	/* 3 bits can be driven by phy3 */
89
+	u8 phy4;	/* 3 bits can be driven by phy4 */
8990 	u8 reserved;	/* mask out the hw driven bits in gpio_request */
9091 };
9192 
....@@ -120,7 +121,8 @@
120121 	else
121122 		chip->shadow &= ~BIT(gpio);
122123 	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
123
-	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
124
+	if (!chip->reserved)
125
+		xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
124126 }
125127 
126128 /**
....@@ -159,9 +161,9 @@
159161 
160162 /**
161163  * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
162
- * @virt: pointer to the remapped register range
164
+ * @chip: Pointer to the xway_stp chip structure
163165  */
164
-static int xway_stp_hw_init(struct xway_stp *chip)
166
+static void xway_stp_hw_init(struct xway_stp *chip)
165167 {
166168 	/* sane defaults */
167169 	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
....@@ -194,23 +196,41 @@
194196 			chip->phy2 << XWAY_STP_PHY2_SHIFT,
195197 			XWAY_STP_CON1);
196198 
199
+	if (of_machine_is_compatible("lantiq,grx390")
200
+	    || of_machine_is_compatible("lantiq,ar10")) {
201
+		xway_stp_w32_mask(chip->virt,
202
+				XWAY_STP_PHY_MASK << XWAY_STP_PHY3_SHIFT,
203
+				chip->phy3 << XWAY_STP_PHY3_SHIFT,
204
+				XWAY_STP_CON1);
205
+	}
206
+
207
+	if (of_machine_is_compatible("lantiq,grx390")) {
208
+		xway_stp_w32_mask(chip->virt,
209
+				XWAY_STP_PHY_MASK << XWAY_STP_PHY4_SHIFT,
210
+				chip->phy4 << XWAY_STP_PHY4_SHIFT,
211
+				XWAY_STP_CON1);
212
+	}
213
+
197214 	/* mask out the hw driven bits in gpio_request */
198
-	chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;
215
+	chip->reserved = (chip->phy4 << 11) | (chip->phy3 << 8) | (chip->phy2 << 5)
216
+		| (chip->phy1 << 2) | chip->dsl;
199217 
200218 	/*
201219 	 * if we have pins that are driven by hw, we need to tell the stp what
202220 	 * clock to use as a timer.
203221 	 */
204
-	if (chip->reserved)
222
+	if (chip->reserved) {
205223 		xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
206224 			XWAY_STP_UPD_FPI, XWAY_STP_CON1);
207
-
208
-	return 0;
225
+		xway_stp_w32_mask(chip->virt, XWAY_STP_SPEED_MASK,
226
+			XWAY_STP_10HZ, XWAY_STP_CON1);
227
+		xway_stp_w32_mask(chip->virt, XWAY_STP_FPIS_MASK,
228
+			XWAY_STP_FPIS_VALUE, XWAY_STP_CON1);
229
+	}
209230 }
210231 
211232 static int xway_stp_probe(struct platform_device *pdev)
212233 {
213
-	struct resource *res;
214234 	u32 shadow, groups, dsl, phy;
215235 	struct xway_stp *chip;
216236 	struct clk *clk;
....@@ -220,8 +240,7 @@
220240 	if (!chip)
221241 		return -ENOMEM;
222242 
223
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224
-	chip->virt = devm_ioremap_resource(&pdev->dev, res);
243
+	chip->virt = devm_platform_ioremap_resource(pdev, 0);
225244 	if (IS_ERR(chip->virt))
226245 		return PTR_ERR(chip->virt);
227246 
....@@ -252,32 +271,51 @@
252271 	/* find out which gpios are controlled by the phys */
253272 	if (of_machine_is_compatible("lantiq,ar9") ||
254273 			of_machine_is_compatible("lantiq,gr9") ||
255
-			of_machine_is_compatible("lantiq,vr9")) {
274
+			of_machine_is_compatible("lantiq,vr9") ||
275
+			of_machine_is_compatible("lantiq,ar10") ||
276
+			of_machine_is_compatible("lantiq,grx390")) {
256277 		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
257278 			chip->phy1 = phy & XWAY_STP_PHY_MASK;
258279 		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
259280 			chip->phy2 = phy & XWAY_STP_PHY_MASK;
260281 	}
261282 
283
+	if (of_machine_is_compatible("lantiq,ar10") ||
284
+			of_machine_is_compatible("lantiq,grx390")) {
285
+		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy3", &phy))
286
+			chip->phy3 = phy & XWAY_STP_PHY_MASK;
287
+	}
288
+
289
+	if (of_machine_is_compatible("lantiq,grx390")) {
290
+		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy4", &phy))
291
+			chip->phy4 = phy & XWAY_STP_PHY_MASK;
292
+	}
293
+
262294 	/* check which edge trigger we should use, default to a falling edge */
263295 	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
264296 		chip->edge = XWAY_STP_FALLING;
265297 
266
-	clk = clk_get(&pdev->dev, NULL);
298
+	clk = devm_clk_get(&pdev->dev, NULL);
267299 	if (IS_ERR(clk)) {
268300 		dev_err(&pdev->dev, "Failed to get clock\n");
269301 		return PTR_ERR(clk);
270302 	}
271
-	clk_enable(clk);
272303 
273
-	ret = xway_stp_hw_init(chip);
274
-	if (!ret)
275
-		ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
304
+	ret = clk_prepare_enable(clk);
305
+	if (ret)
306
+		return ret;
276307 
277
-	if (!ret)
278
-		dev_info(&pdev->dev, "Init done\n");
308
+	xway_stp_hw_init(chip);
279309 
280
-	return ret;
310
+	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
311
+	if (ret) {
312
+		clk_disable_unprepare(clk);
313
+		return ret;
314
+	}
315
+
316
+	dev_info(&pdev->dev, "Init done\n");
317
+
318
+	return 0;
281319 }
282320 
283321 static const struct of_device_id xway_stp_match[] = {