write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/gpio/gpio-pcie-idio-24.c
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@@ -146,15 +146,18 @@
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146
 
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 	/* FET Outputs */
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 	if (offset < 24)
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-		return 0;
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+		return GPIO_LINE_DIRECTION_OUT;
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 	/* Isolated Inputs */
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 	if (offset < 48)
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-		return 1;
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+		return GPIO_LINE_DIRECTION_IN;
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 	/* TTL/CMOS I/O */
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 	/* OUT MODE = 1 when TTL/CMOS Output Mode is set */
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-	return !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask);
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+	if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
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+		return GPIO_LINE_DIRECTION_OUT;
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+
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+	return GPIO_LINE_DIRECTION_IN;
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 }
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 static int idio_24_gpio_direction_input(struct gpio_chip *chip,
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@@ -240,52 +243,34 @@
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 	unsigned long *mask, unsigned long *bits)
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 {
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 	struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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-	size_t i;
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-	const unsigned int gpio_reg_size = 8;
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-	unsigned int bits_offset;
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-	size_t word_index;
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-	unsigned int word_offset;
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-	unsigned long word_mask;
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-	const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
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-	unsigned long port_state;
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+	unsigned long offset;
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+	unsigned long gpio_mask;
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 	void __iomem *ports[] = {
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 		&idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
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 		&idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7,
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 		&idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23,
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 	};
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+	size_t index;
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+	unsigned long port_state;
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 	const unsigned long out_mode_mask = BIT(1);
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256
 
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 	/* clear bits array to a clean slate */
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 	bitmap_zero(bits, chip->ngpio);
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259
 
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-	/* get bits are evaluated a gpio port register at a time */
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-	for (i = 0; i < ARRAY_SIZE(ports) + 1; i++) {
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-		/* gpio offset in bits array */
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-		bits_offset = i * gpio_reg_size;
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-
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-		/* word index for bits array */
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-		word_index = BIT_WORD(bits_offset);
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-
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-		/* gpio offset within current word of bits array */
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-		word_offset = bits_offset % BITS_PER_LONG;
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-
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-		/* mask of get bits for current gpio within current word */
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-		word_mask = mask[word_index] & (port_mask << word_offset);
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-		if (!word_mask) {
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-			/* no get bits in this port so skip to next one */
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-			continue;
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-		}
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+	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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+		index = offset / 8;
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262
 
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 		/* read bits from current gpio port (port 6 is TTL GPIO) */
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-		if (i < 6)
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-			port_state = ioread8(ports[i]);
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+		if (index < 6)
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+			port_state = ioread8(ports[index]);
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 		else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
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 			port_state = ioread8(&idio24gpio->reg->ttl_out0_7);
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 		else
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 			port_state = ioread8(&idio24gpio->reg->ttl_in0_7);
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270
 
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-		/* store acquired bits at respective bits array offset */
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-		bits[word_index] |= port_state << word_offset;
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+		port_state &= gpio_mask;
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+
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+		bitmap_set_value8(bits, port_state, offset);
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 	}
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275
 
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 	return 0;
..
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@@ -336,59 +321,48 @@
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 	unsigned long *mask, unsigned long *bits)
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 {
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 	struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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-	size_t i;
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-	unsigned long bits_offset;
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+	unsigned long offset;
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 	unsigned long gpio_mask;
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-	const unsigned int gpio_reg_size = 8;
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-	const unsigned long port_mask = GENMASK(gpio_reg_size, 0);
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-	unsigned long flags;
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-	unsigned int out_state;
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 	void __iomem *ports[] = {
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 		&idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
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328
 		&idio24gpio->reg->out16_23
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 	};
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+	size_t index;
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+	unsigned long bitmask;
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+	unsigned long flags;
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+	unsigned long out_state;
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 	const unsigned long out_mode_mask = BIT(1);
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-	const unsigned int ttl_offset = 48;
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-	const size_t ttl_i = BIT_WORD(ttl_offset);
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-	const unsigned int word_offset = ttl_offset % BITS_PER_LONG;
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-	const unsigned long ttl_mask = (mask[ttl_i] >> word_offset) & port_mask;
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-	const unsigned long ttl_bits = (bits[ttl_i] >> word_offset) & ttl_mask;
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335
 
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-	/* set bits are processed a gpio port register at a time */
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-	for (i = 0; i < ARRAY_SIZE(ports); i++) {
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-		/* gpio offset in bits array */
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-		bits_offset = i * gpio_reg_size;
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+	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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+		index = offset / 8;
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338
 
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-		/* check if any set bits for current port */
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-		gpio_mask = (*mask >> bits_offset) & port_mask;
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-		if (!gpio_mask) {
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-			/* no set bits for this port so move on to next port */
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-			continue;
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-		}
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+		bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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340
 
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 		raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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342
 
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-		/* process output lines */
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-		out_state = ioread8(ports[i]) & ~gpio_mask;
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-		out_state |= (*bits >> bits_offset) & gpio_mask;
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-		iowrite8(out_state, ports[i]);
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+		/* read bits from current gpio port (port 6 is TTL GPIO) */
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+		if (index < 6) {
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+			out_state = ioread8(ports[index]);
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+		} else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) {
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+			out_state = ioread8(&idio24gpio->reg->ttl_out0_7);
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+		} else {
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+			/* skip TTL GPIO if set for input */
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+			raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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+			continue;
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+		}
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+
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+		/* set requested bit states */
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+		out_state &= ~gpio_mask;
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+		out_state |= bitmask;
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+
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+		/* write bits for current gpio port (port 6 is TTL GPIO) */
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+		if (index < 6)
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+			iowrite8(out_state, ports[index]);
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+		else
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+			iowrite8(out_state, &idio24gpio->reg->ttl_out0_7);
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363
 
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 		raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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 	}
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-
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-	/* check if setting TTL lines and if they are in output mode */
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-	if (!ttl_mask || !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask))
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-		return;
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-
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-	/* handle TTL output */
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-	raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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-
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-	/* process output lines */
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-	out_state = ioread8(&idio24gpio->reg->ttl_out0_7) & ~ttl_mask;
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-	out_state |= ttl_bits;
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-	iowrite8(out_state, &idio24gpio->reg->ttl_out0_7);
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-
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-	raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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 }
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367
 
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 static void idio_24_irq_ack(struct irq_data *data)
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@@ -526,6 +500,7 @@
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 	const size_t pci_plx_bar_index = 1;
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501
 	const size_t pci_bar_index = 2;
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 	const char *const name = pci_name(pdev);
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+	struct gpio_irq_chip *girq;
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504
 
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 	idio24gpio = devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL);
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 	if (!idio24gpio)
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@@ -560,6 +535,15 @@
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 	idio24gpio->chip.set = idio_24_gpio_set;
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 	idio24gpio->chip.set_multiple = idio_24_gpio_set_multiple;
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537
 
538
+	girq = &idio24gpio->chip.irq;
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+	girq->chip = &idio_24_irqchip;
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+	/* This will let us handle the parent IRQ in the driver */
541
+	girq->parent_handler = NULL;
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+	girq->num_parents = 0;
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+	girq->parents = NULL;
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+	girq->default_type = IRQ_TYPE_NONE;
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+	girq->handler = handle_edge_irq;
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+
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547
 	raw_spin_lock_init(&idio24gpio->lock);
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548
 
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 	/* Software board reset */
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@@ -574,13 +558,6 @@
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 	err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio);
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 	if (err) {
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 		dev_err(dev, "GPIO registering failed (%d)\n", err);
577
-		return err;
578
-	}
579
-
580
-	err = gpiochip_irqchip_add(&idio24gpio->chip, &idio_24_irqchip, 0,
581
-		handle_edge_irq, IRQ_TYPE_NONE);
582
-	if (err) {
583
-		dev_err(dev, "Could not add irqchip (%d)\n", err);
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 		return err;
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 	}
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563