~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Support functions for OMAP GPIO
3	4	*
..	..	@@ -6,10 +7,6 @@
6	7	*
7	8	* Copyright (C) 2009 Texas Instruments
8	9	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9		- *
10		- * This program is free software; you can redistribute it and/or modify
11		- * it under the terms of the GNU General Public License version 2 as
12		- * published by the Free Software Foundation.
13	10	*/
14	11
15	12	#include <linux/init.h>
..	..	@@ -19,6 +16,7 @@
19	16	#include <linux/err.h>
20	17	#include <linux/clk.h>
21	18	#include <linux/io.h>
	19	+#include <linux/cpu_pm.h>
22	20	#include <linux/device.h>
23	21	#include <linux/pm_runtime.h>
24	22	#include <linux/pm.h>
..	..	@@ -28,12 +26,10 @@
28	26	#include <linux/bitops.h>
29	27	#include <linux/platform_data/gpio-omap.h>
30	28
31		-#define OFF_MODE 1
32	29	#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33	30
34		-static LIST_HEAD(omap_gpio_list);
35		-
36	31	struct gpio_regs {
	32	+ u32 sysconfig;
37	33	u32 irqenable1;
38	34	u32 irqenable2;
39	35	u32 wake_en;
..	..	@@ -49,8 +45,9 @@
49	45	};
50	46
51	47	struct gpio_bank {
52		- struct list_head node;
53	48	void __iomem *base;
	49	+ const struct omap_gpio_reg_offs *regs;
	50	+
54	51	int irq;
55	52	u32 non_wakeup_gpios;
56	53	u32 enabled_non_wakeup_gpios;
..	..	@@ -62,6 +59,9 @@
62	59	raw_spinlock_t wa_lock;
63	60	struct gpio_chip chip;
64	61	struct clk *dbck;
	62	+ struct notifier_block nb;
	63	+ unsigned int is_suspended:1;
	64	+ unsigned int needs_resume:1;
65	65	u32 mod_usage;
66	66	u32 irq_usage;
67	67	u32 dbck_enable_mask;
..	..	@@ -73,15 +73,9 @@
73	73	int stride;
74	74	u32 width;
75	75	int context_loss_count;
76		- int power_mode;
77		- bool workaround_enabled;
78	76
79	77	void (set_dataout)(struct gpio_bank bank, unsigned gpio, int enable);
80		- void (set_dataout_multiple)(struct gpio_bank bank,
81		- unsigned long mask, unsigned long bits);
82	78	int (get_context_loss_count)(struct device dev);
83		-
84		- struct omap_gpio_reg_offs *regs;
85	79	};
86	80
87	81	#define GPIO_MOD_CTRL_BIT BIT(0)
..	..	@@ -97,20 +91,25 @@
97	91	return gpiochip_get_data(chip);
98	92	}
99	93
	94	+static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
	95	+{
	96	+ u32 val = readl_relaxed(reg);
	97	+
	98	+ if (set)
	99	+ val \|= mask;
	100	+ else
	101	+ val &= ~mask;
	102	+
	103	+ writel_relaxed(val, reg);
	104	+
	105	+ return val;
	106	+}
	107	+
100	108	static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
101	109	int is_input)
102	110	{
103		- void __iomem *reg = bank->base;
104		- u32 l;
105		-
106		- reg += bank->regs->direction;
107		- l = readl_relaxed(reg);
108		- if (is_input)
109		- l \|= BIT(gpio);
110		- else
111		- l &= ~(BIT(gpio));
112		- writel_relaxed(l, reg);
113		- bank->context.oe = l;
	111	+ bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
	112	+ BIT(gpio), is_input);
114	113	}
115	114
116	115
..	..	@@ -136,88 +135,8 @@
136	135	static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
137	136	int enable)
138	137	{
139		- void __iomem *reg = bank->base + bank->regs->dataout;
140		- u32 gpio_bit = BIT(offset);
141		- u32 l;
142		-
143		- l = readl_relaxed(reg);
144		- if (enable)
145		- l \|= gpio_bit;
146		- else
147		- l &= ~gpio_bit;
148		- writel_relaxed(l, reg);
149		- bank->context.dataout = l;
150		-}
151		-
152		-static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
153		-{
154		- void __iomem *reg = bank->base + bank->regs->datain;
155		-
156		- return (readl_relaxed(reg) & (BIT(offset))) != 0;
157		-}
158		-
159		-static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
160		-{
161		- void __iomem *reg = bank->base + bank->regs->dataout;
162		-
163		- return (readl_relaxed(reg) & (BIT(offset))) != 0;
164		-}
165		-
166		-/* set multiple data out values using dedicate set/clear register */
167		-static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank,
168		- unsigned long *mask,
169		- unsigned long *bits)
170		-{
171		- void __iomem *reg = bank->base;
172		- u32 l;
173		-
174		- l = bits & mask;
175		- writel_relaxed(l, reg + bank->regs->set_dataout);
176		- bank->context.dataout \|= l;
177		-
178		- l = ~bits & mask;
179		- writel_relaxed(l, reg + bank->regs->clr_dataout);
180		- bank->context.dataout &= ~l;
181		-}
182		-
183		-/* set multiple data out values using mask register */
184		-static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank,
185		- unsigned long *mask,
186		- unsigned long *bits)
187		-{
188		- void __iomem *reg = bank->base + bank->regs->dataout;
189		- u32 l = (readl_relaxed(reg) & ~mask) \| (bits & *mask);
190		-
191		- writel_relaxed(l, reg);
192		- bank->context.dataout = l;
193		-}
194		-
195		-static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank,
196		- unsigned long *mask)
197		-{
198		- void __iomem *reg = bank->base + bank->regs->datain;
199		-
200		- return readl_relaxed(reg) & *mask;
201		-}
202		-
203		-static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank,
204		- unsigned long *mask)
205		-{
206		- void __iomem *reg = bank->base + bank->regs->dataout;
207		-
208		- return readl_relaxed(reg) & *mask;
209		-}
210		-
211		-static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
212		-{
213		- int l = readl_relaxed(base + reg);
214		-
215		- if (set)
216		- l \|= mask;
217		- else
218		- l &= ~mask;
219		-
220		- writel_relaxed(l, base + reg);
	138	+ bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
	139	+ BIT(offset), enable);
221	140	}
222	141
223	142	static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
..	..	@@ -261,7 +180,6 @@
261	180	static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
262	181	unsigned debounce)
263	182	{
264		- void __iomem *reg;
265	183	u32 val;
266	184	u32 l;
267	185	bool enable = !!debounce;
..	..	@@ -278,19 +196,11 @@
278	196	l = BIT(offset);
279	197
280	198	clk_enable(bank->dbck);
281		- reg = bank->base + bank->regs->debounce;
282		- writel_relaxed(debounce, reg);
	199	+ writel_relaxed(debounce, bank->base + bank->regs->debounce);
283	200
284		- reg = bank->base + bank->regs->debounce_en;
285		- val = readl_relaxed(reg);
286		-
287		- if (enable)
288		- val \|= l;
289		- else
290		- val &= ~l;
	201	+ val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
291	202	bank->dbck_enable_mask = val;
292	203
293		- writel_relaxed(val, reg);
294	204	clk_disable(bank->dbck);
295	205	/*
296	206	* Enable debounce clock per module.
..	..	@@ -365,14 +275,20 @@
365	275	void __iomem *base = bank->base;
366	276	u32 gpio_bit = BIT(gpio);
367	277
368		- omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
	278	+ omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
369	279	trigger & IRQ_TYPE_LEVEL_LOW);
370		- omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
	280	+ omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
371	281	trigger & IRQ_TYPE_LEVEL_HIGH);
372		- omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
373		- trigger & IRQ_TYPE_EDGE_RISING);
374		- omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
375		- trigger & IRQ_TYPE_EDGE_FALLING);
	282	+
	283	+ /*
	284	+ * We need the edge detection enabled for to allow the GPIO block
	285	+ * to be woken from idle state. Set the appropriate edge detection
	286	+ * in addition to the level detection.
	287	+ */
	288	+ omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
	289	+ trigger & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_LEVEL_HIGH));
	290	+ omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
	291	+ trigger & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_LEVEL_LOW));
376	292
377	293	bank->context.leveldetect0 =
378	294	readl_relaxed(bank->base + bank->regs->leveldetect0);
..	..	@@ -383,11 +299,8 @@
383	299	bank->context.fallingdetect =
384	300	readl_relaxed(bank->base + bank->regs->fallingdetect);
385	301
386		- if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
387		- omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
388		- bank->context.wake_en =
389		- readl_relaxed(bank->base + bank->regs->wkup_en);
390		- }
	302	+ bank->level_mask = bank->context.leveldetect0 \|
	303	+ bank->context.leveldetect1;
391	304
392	305	/* This part needs to be executed always for OMAP{34xx, 44xx} */
393	306	if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
..	..	@@ -402,44 +315,25 @@
402	315	else
403	316	bank->enabled_non_wakeup_gpios &= ~gpio_bit;
404	317	}
405		-
406		- bank->level_mask =
407		- readl_relaxed(bank->base + bank->regs->leveldetect0) \|
408		- readl_relaxed(bank->base + bank->regs->leveldetect1);
409	318	}
410	319
411		-#ifdef CONFIG_ARCH_OMAP1
412	320	/*
413	321	* This only applies to chips that can't do both rising and falling edge
414	322	* detection at once. For all other chips, this function is a noop.
415	323	*/
416	324	static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
417	325	{
418		- void __iomem *reg = bank->base;
419		- u32 l = 0;
	326	+ if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
	327	+ void __iomem *reg = bank->base + bank->regs->irqctrl;
420	328
421		- if (!bank->regs->irqctrl)
422		- return;
423		-
424		- reg += bank->regs->irqctrl;
425		-
426		- l = readl_relaxed(reg);
427		- if ((l >> gpio) & 1)
428		- l &= ~(BIT(gpio));
429		- else
430		- l \|= BIT(gpio);
431		-
432		- writel_relaxed(l, reg);
	329	+ writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
	330	+ }
433	331	}
434		-#else
435		-static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
436		-#endif
437	332
438	333	static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
439	334	unsigned trigger)
440	335	{
441	336	void __iomem *reg = bank->base;
442		- void __iomem *base = bank->base;
443	337	u32 l = 0;
444	338
445	339	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
..	..	@@ -471,11 +365,6 @@
471	365	l \|= 2 << (gpio << 1);
472	366	if (trigger & IRQ_TYPE_EDGE_FALLING)
473	367	l \|= BIT(gpio << 1);
474		-
475		- /* Enable wake-up during idle for dynamic tick */
476		- omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
477		- bank->context.wake_en =
478		- readl_relaxed(bank->base + bank->regs->wkup_en);
479	368	writel_relaxed(l, reg);
480	369	}
481	370	return 0;
..	..	@@ -504,17 +393,6 @@
504	393
505	394	static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
506	395	{
507		- void __iomem *base = bank->base;
508		-
509		- if (bank->regs->wkup_en &&
510		- !LINE_USED(bank->mod_usage, offset) &&
511		- !LINE_USED(bank->irq_usage, offset)) {
512		- /* Disable wake-up during idle for dynamic tick */
513		- omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
514		- bank->context.wake_en =
515		- readl_relaxed(bank->base + bank->regs->wkup_en);
516		- }
517		-
518	396	if (bank->regs->ctrl && !BANK_USED(bank)) {
519	397	void __iomem *reg = bank->base + bank->regs->ctrl;
520	398	u32 ctrl;
..	..	@@ -625,57 +503,39 @@
625	503	return l;
626	504	}
627	505
628		-static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
629		-{
630		- void __iomem *reg = bank->base;
631		- u32 l;
632		-
633		- if (bank->regs->set_irqenable) {
634		- reg += bank->regs->set_irqenable;
635		- l = gpio_mask;
636		- bank->context.irqenable1 \|= gpio_mask;
637		- } else {
638		- reg += bank->regs->irqenable;
639		- l = readl_relaxed(reg);
640		- if (bank->regs->irqenable_inv)
641		- l &= ~gpio_mask;
642		- else
643		- l \|= gpio_mask;
644		- bank->context.irqenable1 = l;
645		- }
646		-
647		- writel_relaxed(l, reg);
648		-}
649		-
650		-static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
651		-{
652		- void __iomem *reg = bank->base;
653		- u32 l;
654		-
655		- if (bank->regs->clr_irqenable) {
656		- reg += bank->regs->clr_irqenable;
657		- l = gpio_mask;
658		- bank->context.irqenable1 &= ~gpio_mask;
659		- } else {
660		- reg += bank->regs->irqenable;
661		- l = readl_relaxed(reg);
662		- if (bank->regs->irqenable_inv)
663		- l \|= gpio_mask;
664		- else
665		- l &= ~gpio_mask;
666		- bank->context.irqenable1 = l;
667		- }
668		-
669		- writel_relaxed(l, reg);
670		-}
671		-
672	506	static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
673	507	unsigned offset, int enable)
674	508	{
675		- if (enable)
676		- omap_enable_gpio_irqbank(bank, BIT(offset));
677		- else
678		- omap_disable_gpio_irqbank(bank, BIT(offset));
	509	+ void __iomem *reg = bank->base;
	510	+ u32 gpio_mask = BIT(offset);
	511	+
	512	+ if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
	513	+ if (enable) {
	514	+ reg += bank->regs->set_irqenable;
	515	+ bank->context.irqenable1 \|= gpio_mask;
	516	+ } else {
	517	+ reg += bank->regs->clr_irqenable;
	518	+ bank->context.irqenable1 &= ~gpio_mask;
	519	+ }
	520	+ writel_relaxed(gpio_mask, reg);
	521	+ } else {
	522	+ bank->context.irqenable1 =
	523	+ omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
	524	+ enable ^ bank->regs->irqenable_inv);
	525	+ }
	526	+
	527	+ /*
	528	+ * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
	529	+ * note requiring correlation between the IRQ enable registers and
	530	+ * the wakeup registers. In any case, we want wakeup from idle
	531	+ * enabled for the GPIOs which support this feature.
	532	+ */
	533	+ if (bank->regs->wkup_en &&
	534	+ (bank->regs->edgectrl1 \|\| !(bank->non_wakeup_gpios & gpio_mask))) {
	535	+ bank->context.wake_en =
	536	+ omap_gpio_rmw(bank->base + bank->regs->wkup_en,
	537	+ gpio_mask, enable);
	538	+ }
679	539	}
680	540
681	541	/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
..	..	@@ -684,48 +544,6 @@
684	544	struct gpio_bank *bank = omap_irq_data_get_bank(d);
685	545
686	546	return irq_set_irq_wake(bank->irq, enable);
687		-}
688		-
689		-static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
690		-{
691		- struct gpio_bank *bank = gpiochip_get_data(chip);
692		- unsigned long flags;
693		-
694		- /*
695		- * If this is the first gpio_request for the bank,
696		- * enable the bank module.
697		- */
698		- if (!BANK_USED(bank))
699		- pm_runtime_get_sync(chip->parent);
700		-
701		- raw_spin_lock_irqsave(&bank->lock, flags);
702		- omap_enable_gpio_module(bank, offset);
703		- bank->mod_usage \|= BIT(offset);
704		- raw_spin_unlock_irqrestore(&bank->lock, flags);
705		-
706		- return 0;
707		-}
708		-
709		-static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
710		-{
711		- struct gpio_bank *bank = gpiochip_get_data(chip);
712		- unsigned long flags;
713		-
714		- raw_spin_lock_irqsave(&bank->lock, flags);
715		- bank->mod_usage &= ~(BIT(offset));
716		- if (!LINE_USED(bank->irq_usage, offset)) {
717		- omap_set_gpio_direction(bank, offset, 1);
718		- omap_clear_gpio_debounce(bank, offset);
719		- }
720		- omap_disable_gpio_module(bank, offset);
721		- raw_spin_unlock_irqrestore(&bank->lock, flags);
722		-
723		- /*
724		- * If this is the last gpio to be freed in the bank,
725		- * disable the bank module.
726		- */
727		- if (!BANK_USED(bank))
728		- pm_runtime_put(chip->parent);
729	547	}
730	548
731	549	/*
..	..	@@ -740,7 +558,7 @@
740	558	static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
741	559	{
742	560	void __iomem *isr_reg = NULL;
743		- u32 enabled, isr, level_mask;
	561	+ u32 enabled, isr, edge;
744	562	unsigned int bit;
745	563	struct gpio_bank *bank = gpiobank;
746	564	unsigned long wa_lock_flags;
..	..	@@ -750,7 +568,9 @@
750	568	if (WARN_ON(!isr_reg))
751	569	goto exit;
752	570
753		- pm_runtime_get_sync(bank->chip.parent);
	571	+ if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
	572	+ "gpio irq%i while runtime suspended?\n", irq))
	573	+ return IRQ_NONE;
754	574
755	575	while (1) {
756	576	raw_spin_lock_irqsave(&bank->lock, lock_flags);
..	..	@@ -758,16 +578,14 @@
758	578	enabled = omap_get_gpio_irqbank_mask(bank);
759	579	isr = readl_relaxed(isr_reg) & enabled;
760	580
761		- if (bank->level_mask)
762		- level_mask = bank->level_mask & enabled;
763		- else
764		- level_mask = 0;
765		-
766		- /* clear edge sensitive interrupts before handler(s) are
767		- called so that we don't miss any interrupt occurred while
768		- executing them */
769		- if (isr & ~level_mask)
770		- omap_clear_gpio_irqbank(bank, isr & ~level_mask);
	581	+ /*
	582	+ * Clear edge sensitive interrupts before calling handler(s)
	583	+ * so subsequent edge transitions are not missed while the
	584	+ * handlers are running.
	585	+ */
	586	+ edge = isr & ~bank->level_mask;
	587	+ if (edge)
	588	+ omap_clear_gpio_irqbank(bank, edge);
771	589
772	590	raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
773	591
..	..	@@ -801,7 +619,6 @@
801	619	}
802	620	}
803	621	exit:
804		- pm_runtime_put(bank->chip.parent);
805	622	return IRQ_HANDLED;
806	623	}
807	624
..	..	@@ -815,8 +632,6 @@
815	632
816	633	if (!LINE_USED(bank->mod_usage, offset))
817	634	omap_set_gpio_direction(bank, offset, 1);
818		- else if (!omap_gpio_is_input(bank, offset))
819		- goto err;
820	635	omap_enable_gpio_module(bank, offset);
821	636	bank->irq_usage \|= BIT(offset);
822	637
..	..	@@ -824,9 +639,6 @@
824	639	omap_gpio_unmask_irq(d);
825	640
826	641	return 0;
827		-err:
828		- raw_spin_unlock_irqrestore(&bank->lock, flags);
829		- return -EINVAL;
830	642	}
831	643
832	644	static void omap_gpio_irq_shutdown(struct irq_data *d)
..	..	@@ -850,28 +662,14 @@
850	662	{
851	663	struct gpio_bank *bank = omap_irq_data_get_bank(data);
852	664
853		- if (!BANK_USED(bank))
854		- pm_runtime_get_sync(bank->chip.parent);
	665	+ pm_runtime_get_sync(bank->chip.parent);
855	666	}
856	667
857	668	static void gpio_irq_bus_sync_unlock(struct irq_data *data)
858	669	{
859	670	struct gpio_bank *bank = omap_irq_data_get_bank(data);
860	671
861		- /*
862		- * If this is the last IRQ to be freed in the bank,
863		- * disable the bank module.
864		- */
865		- if (!BANK_USED(bank))
866		- pm_runtime_put(bank->chip.parent);
867		-}
868		-
869		-static void omap_gpio_ack_irq(struct irq_data *d)
870		-{
871		- struct gpio_bank *bank = omap_irq_data_get_bank(d);
872		- unsigned offset = d->hwirq;
873		-
874		- omap_clear_gpio_irqstatus(bank, offset);
	672	+ pm_runtime_put(bank->chip.parent);
875	673	}
876	674
877	675	static void omap_gpio_mask_irq(struct irq_data *d)
..	..	@@ -915,8 +713,7 @@
915	713
916	714	static int omap_mpuio_suspend_noirq(struct device *dev)
917	715	{
918		- struct platform_device *pdev = to_platform_device(dev);
919		- struct gpio_bank *bank = platform_get_drvdata(pdev);
	716	+ struct gpio_bank *bank = dev_get_drvdata(dev);
920	717	void __iomem *mask_reg = bank->base +
921	718	OMAP_MPUIO_GPIO_MASKIT / bank->stride;
922	719	unsigned long flags;
..	..	@@ -930,8 +727,7 @@
930	727
931	728	static int omap_mpuio_resume_noirq(struct device *dev)
932	729	{
933		- struct platform_device *pdev = to_platform_device(dev);
934		- struct gpio_bank *bank = platform_get_drvdata(pdev);
	730	+ struct gpio_bank *bank = dev_get_drvdata(dev);
935	731	void __iomem *mask_reg = bank->base +
936	732	OMAP_MPUIO_GPIO_MASKIT / bank->stride;
937	733	unsigned long flags;
..	..	@@ -975,19 +771,46 @@
975	771
976	772	/---------------------------------------------------------------------/
977	773
	774	+static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
	775	+{
	776	+ struct gpio_bank *bank = gpiochip_get_data(chip);
	777	+ unsigned long flags;
	778	+
	779	+ pm_runtime_get_sync(chip->parent);
	780	+
	781	+ raw_spin_lock_irqsave(&bank->lock, flags);
	782	+ omap_enable_gpio_module(bank, offset);
	783	+ bank->mod_usage \|= BIT(offset);
	784	+ raw_spin_unlock_irqrestore(&bank->lock, flags);
	785	+
	786	+ return 0;
	787	+}
	788	+
	789	+static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
	790	+{
	791	+ struct gpio_bank *bank = gpiochip_get_data(chip);
	792	+ unsigned long flags;
	793	+
	794	+ raw_spin_lock_irqsave(&bank->lock, flags);
	795	+ bank->mod_usage &= ~(BIT(offset));
	796	+ if (!LINE_USED(bank->irq_usage, offset)) {
	797	+ omap_set_gpio_direction(bank, offset, 1);
	798	+ omap_clear_gpio_debounce(bank, offset);
	799	+ }
	800	+ omap_disable_gpio_module(bank, offset);
	801	+ raw_spin_unlock_irqrestore(&bank->lock, flags);
	802	+
	803	+ pm_runtime_put(chip->parent);
	804	+}
	805	+
978	806	static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
979	807	{
980		- struct gpio_bank *bank;
981		- unsigned long flags;
982		- void __iomem *reg;
983		- int dir;
	808	+ struct gpio_bank *bank = gpiochip_get_data(chip);
984	809
985		- bank = gpiochip_get_data(chip);
986		- reg = bank->base + bank->regs->direction;
987		- raw_spin_lock_irqsave(&bank->lock, flags);
988		- dir = !!(readl_relaxed(reg) & BIT(offset));
989		- raw_spin_unlock_irqrestore(&bank->lock, flags);
990		- return dir;
	810	+ if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
	811	+ return GPIO_LINE_DIRECTION_IN;
	812	+
	813	+ return GPIO_LINE_DIRECTION_OUT;
991	814	}
992	815
993	816	static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
..	..	@@ -1004,14 +827,15 @@
1004	827
1005	828	static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
1006	829	{
1007		- struct gpio_bank *bank;
1008		-
1009		- bank = gpiochip_get_data(chip);
	830	+ struct gpio_bank *bank = gpiochip_get_data(chip);
	831	+ void __iomem *reg;
1010	832
1011	833	if (omap_gpio_is_input(bank, offset))
1012		- return omap_get_gpio_datain(bank, offset);
	834	+ reg = bank->base + bank->regs->datain;
1013	835	else
1014		- return omap_get_gpio_dataout(bank, offset);
	836	+ reg = bank->base + bank->regs->dataout;
	837	+
	838	+ return (readl_relaxed(reg) & BIT(offset)) != 0;
1015	839	}
1016	840
1017	841	static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
..	..	@@ -1031,18 +855,20 @@
1031	855	unsigned long *bits)
1032	856	{
1033	857	struct gpio_bank *bank = gpiochip_get_data(chip);
1034		- void __iomem *reg = bank->base + bank->regs->direction;
1035		- unsigned long in = readl_relaxed(reg), l;
	858	+ void __iomem *base = bank->base;
	859	+ u32 direction, m, val = 0;
1036	860
1037		- *bits = 0;
	861	+ direction = readl_relaxed(base + bank->regs->direction);
1038	862
1039		- l = in & *mask;
1040		- if (l)
1041		- *bits \|= omap_get_gpio_datain_multiple(bank, &l);
	863	+ m = direction & *mask;
	864	+ if (m)
	865	+ val \|= readl_relaxed(base + bank->regs->datain) & m;
1042	866
1043		- l = ~in & *mask;
1044		- if (l)
1045		- *bits \|= omap_get_gpio_dataout_multiple(bank, &l);
	867	+ m = ~direction & *mask;
	868	+ if (m)
	869	+ val \|= readl_relaxed(base + bank->regs->dataout) & m;
	870	+
	871	+ *bits = val;
1046	872
1047	873	return 0;
1048	874	}
..	..	@@ -1072,12 +898,23 @@
1072	898	unsigned long config)
1073	899	{
1074	900	u32 debounce;
	901	+ int ret = -ENOTSUPP;
1075	902
1076		- if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1077		- return -ENOTSUPP;
	903	+ switch (pinconf_to_config_param(config)) {
	904	+ case PIN_CONFIG_BIAS_DISABLE:
	905	+ case PIN_CONFIG_BIAS_PULL_UP:
	906	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	907	+ ret = gpiochip_generic_config(chip, offset, config);
	908	+ break;
	909	+ case PIN_CONFIG_INPUT_DEBOUNCE:
	910	+ debounce = pinconf_to_config_argument(config);
	911	+ ret = omap_gpio_debounce(chip, offset, debounce);
	912	+ break;
	913	+ default:
	914	+ break;
	915	+ }
1078	916
1079		- debounce = pinconf_to_config_argument(config);
1080		- return omap_gpio_debounce(chip, offset, debounce);
	917	+ return ret;
1081	918	}
1082	919
1083	920	static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
..	..	@@ -1095,10 +932,14 @@
1095	932	unsigned long *bits)
1096	933	{
1097	934	struct gpio_bank *bank = gpiochip_get_data(chip);
	935	+ void __iomem *reg = bank->base + bank->regs->dataout;
1098	936	unsigned long flags;
	937	+ u32 l;
1099	938
1100	939	raw_spin_lock_irqsave(&bank->lock, flags);
1101		- bank->set_dataout_multiple(bank, mask, bits);
	940	+ l = (readl_relaxed(reg) & ~mask) \| (bits & *mask);
	941	+ writel_relaxed(l, reg);
	942	+ bank->context.dataout = l;
1102	943	raw_spin_unlock_irqrestore(&bank->lock, flags);
1103	944	}
1104	945
..	..	@@ -1132,9 +973,9 @@
1132	973	return;
1133	974	}
1134	975
1135		- omap_gpio_rmw(base, bank->regs->irqenable, l,
	976	+ omap_gpio_rmw(base + bank->regs->irqenable, l,
1136	977	bank->regs->irqenable_inv);
1137		- omap_gpio_rmw(base, bank->regs->irqstatus, l,
	978	+ omap_gpio_rmw(base + bank->regs->irqstatus, l,
1138	979	!bank->regs->irqenable_inv);
1139	980	if (bank->regs->debounce_en)
1140	981	writel_relaxed(0, base + bank->regs->debounce_en);
..	..	@@ -1197,11 +1038,8 @@
1197	1038	#endif
1198	1039
1199	1040	/* MPUIO is a bit different, reading IRQ status clears it */
1200		- if (bank->is_mpuio) {
1201		- irqc->irq_ack = dummy_irq_chip.irq_ack;
1202		- if (!bank->regs->wkup_en)
1203		- irqc->irq_set_wake = NULL;
1204		- }
	1041	+ if (bank->is_mpuio && !bank->regs->wkup_en)
	1042	+ irqc->irq_set_wake = NULL;
1205	1043
1206	1044	irq = &bank->chip.irq;
1207	1045	irq->chip = irqc;
..	..	@@ -1230,208 +1068,89 @@
1230	1068	return ret;
1231	1069	}
1232	1070
1233		-static const struct of_device_id omap_gpio_match[];
1234		-
1235		-static int omap_gpio_probe(struct platform_device *pdev)
	1071	+static void omap_gpio_init_context(struct gpio_bank *p)
1236	1072	{
1237		- struct device *dev = &pdev->dev;
1238		- struct device_node *node = dev->of_node;
1239		- const struct of_device_id *match;
1240		- const struct omap_gpio_platform_data *pdata;
1241		- struct resource *res;
1242		- struct gpio_bank *bank;
1243		- struct irq_chip *irqc;
1244		- int ret;
	1073	+ const struct omap_gpio_reg_offs *regs = p->regs;
	1074	+ void __iomem *base = p->base;
1245	1075
1246		- match = of_match_device(of_match_ptr(omap_gpio_match), dev);
	1076	+ p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
	1077	+ p->context.ctrl = readl_relaxed(base + regs->ctrl);
	1078	+ p->context.oe = readl_relaxed(base + regs->direction);
	1079	+ p->context.wake_en = readl_relaxed(base + regs->wkup_en);
	1080	+ p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
	1081	+ p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
	1082	+ p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
	1083	+ p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
	1084	+ p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
	1085	+ p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
	1086	+ p->context.dataout = readl_relaxed(base + regs->dataout);
1247	1087
1248		- pdata = match ? match->data : dev_get_platdata(dev);
1249		- if (!pdata)
1250		- return -EINVAL;
1251		-
1252		- bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1253		- if (!bank)
1254		- return -ENOMEM;
1255		-
1256		- irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1257		- if (!irqc)
1258		- return -ENOMEM;
1259		-
1260		- irqc->irq_startup = omap_gpio_irq_startup,
1261		- irqc->irq_shutdown = omap_gpio_irq_shutdown,
1262		- irqc->irq_ack = omap_gpio_ack_irq,
1263		- irqc->irq_mask = omap_gpio_mask_irq,
1264		- irqc->irq_unmask = omap_gpio_unmask_irq,
1265		- irqc->irq_set_type = omap_gpio_irq_type,
1266		- irqc->irq_set_wake = omap_gpio_wake_enable,
1267		- irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1268		- irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1269		- irqc->name = dev_name(&pdev->dev);
1270		- irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1271		-
1272		- bank->irq = platform_get_irq(pdev, 0);
1273		- if (bank->irq <= 0) {
1274		- if (!bank->irq)
1275		- bank->irq = -ENXIO;
1276		- if (bank->irq != -EPROBE_DEFER)
1277		- dev_err(dev,
1278		- "can't get irq resource ret=%d\n", bank->irq);
1279		- return bank->irq;
1280		- }
1281		-
1282		- bank->chip.parent = dev;
1283		- bank->chip.owner = THIS_MODULE;
1284		- bank->dbck_flag = pdata->dbck_flag;
1285		- bank->stride = pdata->bank_stride;
1286		- bank->width = pdata->bank_width;
1287		- bank->is_mpuio = pdata->is_mpuio;
1288		- bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1289		- bank->regs = pdata->regs;
1290		-#ifdef CONFIG_OF_GPIO
1291		- bank->chip.of_node = of_node_get(node);
1292		-#endif
1293		- if (node) {
1294		- if (!of_property_read_bool(node, "ti,gpio-always-on"))
1295		- bank->loses_context = true;
1296		- } else {
1297		- bank->loses_context = pdata->loses_context;
1298		-
1299		- if (bank->loses_context)
1300		- bank->get_context_loss_count =
1301		- pdata->get_context_loss_count;
1302		- }
1303		-
1304		- if (bank->regs->set_dataout && bank->regs->clr_dataout) {
1305		- bank->set_dataout = omap_set_gpio_dataout_reg;
1306		- bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple;
1307		- } else {
1308		- bank->set_dataout = omap_set_gpio_dataout_mask;
1309		- bank->set_dataout_multiple =
1310		- omap_set_gpio_dataout_mask_multiple;
1311		- }
1312		-
1313		- raw_spin_lock_init(&bank->lock);
1314		- raw_spin_lock_init(&bank->wa_lock);
1315		-
1316		- /* Static mapping, never released */
1317		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1318		- bank->base = devm_ioremap_resource(dev, res);
1319		- if (IS_ERR(bank->base)) {
1320		- return PTR_ERR(bank->base);
1321		- }
1322		-
1323		- if (bank->dbck_flag) {
1324		- bank->dbck = devm_clk_get(dev, "dbclk");
1325		- if (IS_ERR(bank->dbck)) {
1326		- dev_err(dev,
1327		- "Could not get gpio dbck. Disable debounce\n");
1328		- bank->dbck_flag = false;
1329		- } else {
1330		- clk_prepare(bank->dbck);
1331		- }
1332		- }
1333		-
1334		- platform_set_drvdata(pdev, bank);
1335		-
1336		- pm_runtime_enable(dev);
1337		- pm_runtime_irq_safe(dev);
1338		- pm_runtime_get_sync(dev);
1339		-
1340		- if (bank->is_mpuio)
1341		- omap_mpuio_init(bank);
1342		-
1343		- omap_gpio_mod_init(bank);
1344		-
1345		- ret = omap_gpio_chip_init(bank, irqc);
1346		- if (ret) {
1347		- pm_runtime_put_sync(dev);
1348		- pm_runtime_disable(dev);
1349		- if (bank->dbck_flag)
1350		- clk_unprepare(bank->dbck);
1351		- return ret;
1352		- }
1353		-
1354		- omap_gpio_show_rev(bank);
1355		-
1356		- pm_runtime_put(dev);
1357		-
1358		- list_add_tail(&bank->node, &omap_gpio_list);
1359		-
1360		- return 0;
	1088	+ p->context_valid = true;
1361	1089	}
1362	1090
1363		-static int omap_gpio_remove(struct platform_device *pdev)
	1091	+static void omap_gpio_restore_context(struct gpio_bank *bank)
1364	1092	{
1365		- struct gpio_bank *bank = platform_get_drvdata(pdev);
	1093	+ const struct omap_gpio_reg_offs *regs = bank->regs;
	1094	+ void __iomem *base = bank->base;
1366	1095
1367		- list_del(&bank->node);
1368		- gpiochip_remove(&bank->chip);
1369		- pm_runtime_disable(&pdev->dev);
1370		- if (bank->dbck_flag)
1371		- clk_unprepare(bank->dbck);
	1096	+ writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
	1097	+ writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
	1098	+ writel_relaxed(bank->context.ctrl, base + regs->ctrl);
	1099	+ writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
	1100	+ writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
	1101	+ writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
	1102	+ writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
	1103	+ writel_relaxed(bank->context.dataout, base + regs->dataout);
	1104	+ writel_relaxed(bank->context.oe, base + regs->direction);
1372	1105
1373		- return 0;
	1106	+ if (bank->dbck_enable_mask) {
	1107	+ writel_relaxed(bank->context.debounce, base + regs->debounce);
	1108	+ writel_relaxed(bank->context.debounce_en,
	1109	+ base + regs->debounce_en);
	1110	+ }
	1111	+
	1112	+ writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
	1113	+ writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1374	1114	}
1375	1115
1376		-#ifdef CONFIG_ARCH_OMAP2PLUS
1377		-
1378		-#if defined(CONFIG_PM)
1379		-static void omap_gpio_restore_context(struct gpio_bank *bank);
1380		-
1381		-static int omap_gpio_runtime_suspend(struct device *dev)
	1116	+static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1382	1117	{
1383		- struct platform_device *pdev = to_platform_device(dev);
1384		- struct gpio_bank *bank = platform_get_drvdata(pdev);
1385		- u32 l1 = 0, l2 = 0;
1386		- unsigned long flags;
1387		- u32 wake_low, wake_hi;
	1118	+ struct device *dev = bank->chip.parent;
	1119	+ void __iomem *base = bank->base;
	1120	+ u32 mask, nowake;
1388	1121
1389		- raw_spin_lock_irqsave(&bank->lock, flags);
	1122	+ bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1390	1123
1391		- /*
1392		- * Only edges can generate a wakeup event to the PRCM.
1393		- *
1394		- * Therefore, ensure any wake-up capable GPIOs have
1395		- * edge-detection enabled before going idle to ensure a wakeup
1396		- * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1397		- * NDA TRM 25.5.3.1)
1398		- *
1399		- * The normal values will be restored upon ->runtime_resume()
1400		- * by writing back the values saved in bank->context.
1401		- */
1402		- wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1403		- if (wake_low)
1404		- writel_relaxed(wake_low \| bank->context.fallingdetect,
1405		- bank->base + bank->regs->fallingdetect);
1406		- wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1407		- if (wake_hi)
1408		- writel_relaxed(wake_hi \| bank->context.risingdetect,
1409		- bank->base + bank->regs->risingdetect);
	1124	+ /* Save syconfig, it's runtime value can be different from init value */
	1125	+ if (bank->loses_context)
	1126	+ bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1410	1127
1411	1128	if (!bank->enabled_non_wakeup_gpios)
1412	1129	goto update_gpio_context_count;
1413	1130
1414		- if (bank->power_mode != OFF_MODE) {
1415		- bank->power_mode = 0;
	1131	+ /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
	1132	+ mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
	1133	+ mask &= ~bank->context.risingdetect;
	1134	+ bank->saved_datain \|= mask;
	1135	+
	1136	+ /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
	1137	+ mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
	1138	+ mask &= ~bank->context.fallingdetect;
	1139	+ bank->saved_datain &= ~mask;
	1140	+
	1141	+ if (!may_lose_context)
1416	1142	goto update_gpio_context_count;
1417		- }
	1143	+
1418	1144	/*
1419		- * If going to OFF, remove triggering for all
	1145	+ * If going to OFF, remove triggering for all wkup domain
1420	1146	* non-wakeup GPIOs. Otherwise spurious IRQs will be
1421	1147	* generated. See OMAP2420 Errata item 1.101.
1422	1148	*/
1423		- bank->saved_datain = readl_relaxed(bank->base +
1424		- bank->regs->datain);
1425		- l1 = bank->context.fallingdetect;
1426		- l2 = bank->context.risingdetect;
1427		-
1428		- l1 &= ~bank->enabled_non_wakeup_gpios;
1429		- l2 &= ~bank->enabled_non_wakeup_gpios;
1430		-
1431		- writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1432		- writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1433		-
1434		- bank->workaround_enabled = true;
	1149	+ if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
	1150	+ nowake = bank->enabled_non_wakeup_gpios;
	1151	+ omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
	1152	+ omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
	1153	+ }
1435	1154
1436	1155	update_gpio_context_count:
1437	1156	if (bank->get_context_loss_count)
..	..	@@ -1439,22 +1158,13 @@
1439	1158	bank->get_context_loss_count(dev);
1440	1159
1441	1160	omap_gpio_dbck_disable(bank);
1442		- raw_spin_unlock_irqrestore(&bank->lock, flags);
1443		-
1444		- return 0;
1445	1161	}
1446	1162
1447		-static void omap_gpio_init_context(struct gpio_bank *p);
1448		-
1449		-static int omap_gpio_runtime_resume(struct device *dev)
	1163	+static void omap_gpio_unidle(struct gpio_bank *bank)
1450	1164	{
1451		- struct platform_device *pdev = to_platform_device(dev);
1452		- struct gpio_bank *bank = platform_get_drvdata(pdev);
	1165	+ struct device *dev = bank->chip.parent;
1453	1166	u32 l = 0, gen, gen0, gen1;
1454		- unsigned long flags;
1455	1167	int c;
1456		-
1457		- raw_spin_lock_irqsave(&bank->lock, flags);
1458	1168
1459	1169	/*
1460	1170	* On the first resume during the probe, the context has not
..	..	@@ -1471,17 +1181,6 @@
1471	1181
1472	1182	omap_gpio_dbck_enable(bank);
1473	1183
1474		- /*
1475		- * In ->runtime_suspend(), level-triggered, wakeup-enabled
1476		- * GPIOs were set to edge trigger also in order to be able to
1477		- * generate a PRCM wakeup. Here we restore the
1478		- * pre-runtime_suspend() values for edge triggering.
1479		- */
1480		- writel_relaxed(bank->context.fallingdetect,
1481		- bank->base + bank->regs->fallingdetect);
1482		- writel_relaxed(bank->context.risingdetect,
1483		- bank->base + bank->regs->risingdetect);
1484		-
1485	1184	if (bank->loses_context) {
1486	1185	if (!bank->get_context_loss_count) {
1487	1186	omap_gpio_restore_context(bank);
..	..	@@ -1490,15 +1189,15 @@
1490	1189	if (c != bank->context_loss_count) {
1491	1190	omap_gpio_restore_context(bank);
1492	1191	} else {
1493		- raw_spin_unlock_irqrestore(&bank->lock, flags);
1494		- return 0;
	1192	+ return;
1495	1193	}
1496	1194	}
1497		- }
1498		-
1499		- if (!bank->workaround_enabled) {
1500		- raw_spin_unlock_irqrestore(&bank->lock, flags);
1501		- return 0;
	1195	+ } else {
	1196	+ /* Restore changes done for OMAP2420 errata 1.101 */
	1197	+ writel_relaxed(bank->context.fallingdetect,
	1198	+ bank->base + bank->regs->fallingdetect);
	1199	+ writel_relaxed(bank->context.risingdetect,
	1200	+ bank->base + bank->regs->risingdetect);
1502	1201	}
1503	1202
1504	1203	l = readl_relaxed(bank->base + bank->regs->datain);
..	..	@@ -1550,114 +1249,47 @@
1550	1249	writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1551	1250	writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1552	1251	}
	1252	+}
1553	1253
1554		- bank->workaround_enabled = false;
	1254	+static int gpio_omap_cpu_notifier(struct notifier_block *nb,
	1255	+ unsigned long cmd, void *v)
	1256	+{
	1257	+ struct gpio_bank *bank;
	1258	+ unsigned long flags;
	1259	+ int ret = NOTIFY_OK;
	1260	+ u32 isr, mask;
	1261	+
	1262	+ bank = container_of(nb, struct gpio_bank, nb);
	1263	+
	1264	+ raw_spin_lock_irqsave(&bank->lock, flags);
	1265	+ if (bank->is_suspended)
	1266	+ goto out_unlock;
	1267	+
	1268	+ switch (cmd) {
	1269	+ case CPU_CLUSTER_PM_ENTER:
	1270	+ mask = omap_get_gpio_irqbank_mask(bank);
	1271	+ isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
	1272	+ if (isr) {
	1273	+ ret = NOTIFY_BAD;
	1274	+ break;
	1275	+ }
	1276	+ omap_gpio_idle(bank, true);
	1277	+ break;
	1278	+ case CPU_CLUSTER_PM_ENTER_FAILED:
	1279	+ case CPU_CLUSTER_PM_EXIT:
	1280	+ omap_gpio_unidle(bank);
	1281	+ break;
	1282	+ }
	1283	+
	1284	+out_unlock:
1555	1285	raw_spin_unlock_irqrestore(&bank->lock, flags);
1556	1286
1557		- return 0;
1558		-}
1559		-#endif /* CONFIG_PM */
1560		-
1561		-#if IS_BUILTIN(CONFIG_GPIO_OMAP)
1562		-void omap2_gpio_prepare_for_idle(int pwr_mode)
1563		-{
1564		- struct gpio_bank *bank;
1565		-
1566		- list_for_each_entry(bank, &omap_gpio_list, node) {
1567		- if (!BANK_USED(bank) \|\| !bank->loses_context)
1568		- continue;
1569		-
1570		- bank->power_mode = pwr_mode;
1571		-
1572		- pm_runtime_put_sync_suspend(bank->chip.parent);
1573		- }
	1287	+ return ret;
1574	1288	}
1575	1289
1576		-void omap2_gpio_resume_after_idle(void)
1577		-{
1578		- struct gpio_bank *bank;
1579		-
1580		- list_for_each_entry(bank, &omap_gpio_list, node) {
1581		- if (!BANK_USED(bank) \|\| !bank->loses_context)
1582		- continue;
1583		-
1584		- pm_runtime_get_sync(bank->chip.parent);
1585		- }
1586		-}
1587		-#endif
1588		-
1589		-#if defined(CONFIG_PM)
1590		-static void omap_gpio_init_context(struct gpio_bank *p)
1591		-{
1592		- struct omap_gpio_reg_offs *regs = p->regs;
1593		- void __iomem *base = p->base;
1594		-
1595		- p->context.ctrl = readl_relaxed(base + regs->ctrl);
1596		- p->context.oe = readl_relaxed(base + regs->direction);
1597		- p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1598		- p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1599		- p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1600		- p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1601		- p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1602		- p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1603		- p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1604		-
1605		- if (regs->set_dataout && p->regs->clr_dataout)
1606		- p->context.dataout = readl_relaxed(base + regs->set_dataout);
1607		- else
1608		- p->context.dataout = readl_relaxed(base + regs->dataout);
1609		-
1610		- p->context_valid = true;
1611		-}
1612		-
1613		-static void omap_gpio_restore_context(struct gpio_bank *bank)
1614		-{
1615		- writel_relaxed(bank->context.wake_en,
1616		- bank->base + bank->regs->wkup_en);
1617		- writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1618		- writel_relaxed(bank->context.leveldetect0,
1619		- bank->base + bank->regs->leveldetect0);
1620		- writel_relaxed(bank->context.leveldetect1,
1621		- bank->base + bank->regs->leveldetect1);
1622		- writel_relaxed(bank->context.risingdetect,
1623		- bank->base + bank->regs->risingdetect);
1624		- writel_relaxed(bank->context.fallingdetect,
1625		- bank->base + bank->regs->fallingdetect);
1626		- if (bank->regs->set_dataout && bank->regs->clr_dataout)
1627		- writel_relaxed(bank->context.dataout,
1628		- bank->base + bank->regs->set_dataout);
1629		- else
1630		- writel_relaxed(bank->context.dataout,
1631		- bank->base + bank->regs->dataout);
1632		- writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1633		-
1634		- if (bank->dbck_enable_mask) {
1635		- writel_relaxed(bank->context.debounce, bank->base +
1636		- bank->regs->debounce);
1637		- writel_relaxed(bank->context.debounce_en,
1638		- bank->base + bank->regs->debounce_en);
1639		- }
1640		-
1641		- writel_relaxed(bank->context.irqenable1,
1642		- bank->base + bank->regs->irqenable);
1643		- writel_relaxed(bank->context.irqenable2,
1644		- bank->base + bank->regs->irqenable2);
1645		-}
1646		-#endif /* CONFIG_PM */
1647		-#else
1648		-#define omap_gpio_runtime_suspend NULL
1649		-#define omap_gpio_runtime_resume NULL
1650		-static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1651		-#endif
1652		-
1653		-static const struct dev_pm_ops gpio_pm_ops = {
1654		- SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1655		- NULL)
1656		-};
1657		-
1658		-#if defined(CONFIG_OF)
1659		-static struct omap_gpio_reg_offs omap2_gpio_regs = {
	1290	+static const struct omap_gpio_reg_offs omap2_gpio_regs = {
1660	1291	.revision = OMAP24XX_GPIO_REVISION,
	1292	+ .sysconfig = OMAP24XX_GPIO_SYSCONFIG,
1661	1293	.direction = OMAP24XX_GPIO_OE,
1662	1294	.datain = OMAP24XX_GPIO_DATAIN,
1663	1295	.dataout = OMAP24XX_GPIO_DATAOUT,
..	..	@@ -1679,8 +1311,9 @@
1679	1311	.fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1680	1312	};
1681	1313
1682		-static struct omap_gpio_reg_offs omap4_gpio_regs = {
	1314	+static const struct omap_gpio_reg_offs omap4_gpio_regs = {
1683	1315	.revision = OMAP4_GPIO_REVISION,
	1316	+ .sysconfig = OMAP4_GPIO_SYSCONFIG,
1684	1317	.direction = OMAP4_GPIO_OE,
1685	1318	.datain = OMAP4_GPIO_DATAIN,
1686	1319	.dataout = OMAP4_GPIO_DATAOUT,
..	..	@@ -1738,7 +1371,196 @@
1738	1371	{ },
1739	1372	};
1740	1373	MODULE_DEVICE_TABLE(of, omap_gpio_match);
	1374	+
	1375	+static int omap_gpio_probe(struct platform_device *pdev)
	1376	+{
	1377	+ struct device *dev = &pdev->dev;
	1378	+ struct device_node *node = dev->of_node;
	1379	+ const struct of_device_id *match;
	1380	+ const struct omap_gpio_platform_data *pdata;
	1381	+ struct gpio_bank *bank;
	1382	+ struct irq_chip *irqc;
	1383	+ int ret;
	1384	+
	1385	+ match = of_match_device(of_match_ptr(omap_gpio_match), dev);
	1386	+
	1387	+ pdata = match ? match->data : dev_get_platdata(dev);
	1388	+ if (!pdata)
	1389	+ return -EINVAL;
	1390	+
	1391	+ bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
	1392	+ if (!bank)
	1393	+ return -ENOMEM;
	1394	+
	1395	+ irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
	1396	+ if (!irqc)
	1397	+ return -ENOMEM;
	1398	+
	1399	+ irqc->irq_startup = omap_gpio_irq_startup,
	1400	+ irqc->irq_shutdown = omap_gpio_irq_shutdown,
	1401	+ irqc->irq_ack = dummy_irq_chip.irq_ack,
	1402	+ irqc->irq_mask = omap_gpio_mask_irq,
	1403	+ irqc->irq_unmask = omap_gpio_unmask_irq,
	1404	+ irqc->irq_set_type = omap_gpio_irq_type,
	1405	+ irqc->irq_set_wake = omap_gpio_wake_enable,
	1406	+ irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
	1407	+ irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
	1408	+ irqc->name = dev_name(&pdev->dev);
	1409	+ irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
	1410	+ irqc->parent_device = dev;
	1411	+
	1412	+ bank->irq = platform_get_irq(pdev, 0);
	1413	+ if (bank->irq <= 0) {
	1414	+ if (!bank->irq)
	1415	+ bank->irq = -ENXIO;
	1416	+ return dev_err_probe(dev, bank->irq, "can't get irq resource\n");
	1417	+ }
	1418	+
	1419	+ bank->chip.parent = dev;
	1420	+ bank->chip.owner = THIS_MODULE;
	1421	+ bank->dbck_flag = pdata->dbck_flag;
	1422	+ bank->stride = pdata->bank_stride;
	1423	+ bank->width = pdata->bank_width;
	1424	+ bank->is_mpuio = pdata->is_mpuio;
	1425	+ bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
	1426	+ bank->regs = pdata->regs;
	1427	+#ifdef CONFIG_OF_GPIO
	1428	+ bank->chip.of_node = of_node_get(node);
1741	1429	#endif
	1430	+
	1431	+ if (node) {
	1432	+ if (!of_property_read_bool(node, "ti,gpio-always-on"))
	1433	+ bank->loses_context = true;
	1434	+ } else {
	1435	+ bank->loses_context = pdata->loses_context;
	1436	+
	1437	+ if (bank->loses_context)
	1438	+ bank->get_context_loss_count =
	1439	+ pdata->get_context_loss_count;
	1440	+ }
	1441	+
	1442	+ if (bank->regs->set_dataout && bank->regs->clr_dataout)
	1443	+ bank->set_dataout = omap_set_gpio_dataout_reg;
	1444	+ else
	1445	+ bank->set_dataout = omap_set_gpio_dataout_mask;
	1446	+
	1447	+ raw_spin_lock_init(&bank->lock);
	1448	+ raw_spin_lock_init(&bank->wa_lock);
	1449	+
	1450	+ /* Static mapping, never released */
	1451	+ bank->base = devm_platform_ioremap_resource(pdev, 0);
	1452	+ if (IS_ERR(bank->base)) {
	1453	+ return PTR_ERR(bank->base);
	1454	+ }
	1455	+
	1456	+ if (bank->dbck_flag) {
	1457	+ bank->dbck = devm_clk_get(dev, "dbclk");
	1458	+ if (IS_ERR(bank->dbck)) {
	1459	+ dev_err(dev,
	1460	+ "Could not get gpio dbck. Disable debounce\n");
	1461	+ bank->dbck_flag = false;
	1462	+ } else {
	1463	+ clk_prepare(bank->dbck);
	1464	+ }
	1465	+ }
	1466	+
	1467	+ platform_set_drvdata(pdev, bank);
	1468	+
	1469	+ pm_runtime_enable(dev);
	1470	+ pm_runtime_get_sync(dev);
	1471	+
	1472	+ if (bank->is_mpuio)
	1473	+ omap_mpuio_init(bank);
	1474	+
	1475	+ omap_gpio_mod_init(bank);
	1476	+
	1477	+ ret = omap_gpio_chip_init(bank, irqc);
	1478	+ if (ret) {
	1479	+ pm_runtime_put_sync(dev);
	1480	+ pm_runtime_disable(dev);
	1481	+ if (bank->dbck_flag)
	1482	+ clk_unprepare(bank->dbck);
	1483	+ return ret;
	1484	+ }
	1485	+
	1486	+ omap_gpio_show_rev(bank);
	1487	+
	1488	+ bank->nb.notifier_call = gpio_omap_cpu_notifier;
	1489	+ cpu_pm_register_notifier(&bank->nb);
	1490	+
	1491	+ pm_runtime_put(dev);
	1492	+
	1493	+ return 0;
	1494	+}
	1495	+
	1496	+static int omap_gpio_remove(struct platform_device *pdev)
	1497	+{
	1498	+ struct gpio_bank *bank = platform_get_drvdata(pdev);
	1499	+
	1500	+ cpu_pm_unregister_notifier(&bank->nb);
	1501	+ gpiochip_remove(&bank->chip);
	1502	+ pm_runtime_disable(&pdev->dev);
	1503	+ if (bank->dbck_flag)
	1504	+ clk_unprepare(bank->dbck);
	1505	+
	1506	+ return 0;
	1507	+}
	1508	+
	1509	+static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
	1510	+{
	1511	+ struct gpio_bank *bank = dev_get_drvdata(dev);
	1512	+ unsigned long flags;
	1513	+
	1514	+ raw_spin_lock_irqsave(&bank->lock, flags);
	1515	+ omap_gpio_idle(bank, true);
	1516	+ bank->is_suspended = true;
	1517	+ raw_spin_unlock_irqrestore(&bank->lock, flags);
	1518	+
	1519	+ return 0;
	1520	+}
	1521	+
	1522	+static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
	1523	+{
	1524	+ struct gpio_bank *bank = dev_get_drvdata(dev);
	1525	+ unsigned long flags;
	1526	+
	1527	+ raw_spin_lock_irqsave(&bank->lock, flags);
	1528	+ omap_gpio_unidle(bank);
	1529	+ bank->is_suspended = false;
	1530	+ raw_spin_unlock_irqrestore(&bank->lock, flags);
	1531	+
	1532	+ return 0;
	1533	+}
	1534	+
	1535	+static int __maybe_unused omap_gpio_suspend(struct device *dev)
	1536	+{
	1537	+ struct gpio_bank *bank = dev_get_drvdata(dev);
	1538	+
	1539	+ if (bank->is_suspended)
	1540	+ return 0;
	1541	+
	1542	+ bank->needs_resume = 1;
	1543	+
	1544	+ return omap_gpio_runtime_suspend(dev);
	1545	+}
	1546	+
	1547	+static int __maybe_unused omap_gpio_resume(struct device *dev)
	1548	+{
	1549	+ struct gpio_bank *bank = dev_get_drvdata(dev);
	1550	+
	1551	+ if (!bank->needs_resume)
	1552	+ return 0;
	1553	+
	1554	+ bank->needs_resume = 0;
	1555	+
	1556	+ return omap_gpio_runtime_resume(dev);
	1557	+}
	1558	+
	1559	+static const struct dev_pm_ops gpio_pm_ops = {
	1560	+ SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
	1561	+ NULL)
	1562	+ SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
	1563	+};
1742	1564
1743	1565	static struct platform_driver omap_gpio_driver = {
1744	1566	.probe = omap_gpio_probe,
..	..	@@ -1746,7 +1568,7 @@
1746	1568	.driver = {
1747	1569	.name = "omap_gpio",
1748	1570	.pm = &gpio_pm_ops,
1749		- .of_match_table = of_match_ptr(omap_gpio_match),
	1571	+ .of_match_table = omap_gpio_match,
1750	1572	},
1751	1573	};
1752	1574