write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/gpio/gpio-mpc8xxx.c
..
..
@@ -22,6 +22,7 @@
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 #include <linux/irq.h>
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 #include <linux/gpio/driver.h>
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 #include <linux/bitops.h>
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+#include <linux/interrupt.h>
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26
 
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 #define MPC8XXX_GPIO_PINS	32
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28
 
..
..
@@ -32,6 +33,7 @@
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 #define GPIO_IMR		0x10
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 #define GPIO_ICR		0x14
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 #define GPIO_ICR2		0x18
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+#define GPIO_IBE		0x18
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 struct mpc8xxx_gpio_chip {
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 	struct gpio_chip	gc;
..
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@@ -105,20 +107,19 @@
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 		return -ENXIO;
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 }
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-static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
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+static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
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 {
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-	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
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-	struct irq_chip *chip = irq_desc_get_chip(desc);
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+	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
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 	struct gpio_chip *gc = &mpc8xxx_gc->gc;
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-	unsigned int mask;
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+	unsigned long mask;
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+	int i;
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 	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
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 		& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
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-	if (mask)
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-		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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-						     32 - ffs(mask)));
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-	if (chip->irq_eoi)
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-		chip->irq_eoi(&desc->irq_data);
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+	for_each_set_bit(i, &mask, 32)
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+		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
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+
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+	return IRQ_HANDLED;
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 }
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 static void mpc8xxx_irq_unmask(struct irq_data *d)
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@@ -168,6 +169,7 @@
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 	switch (flow_type) {
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 	case IRQ_TYPE_EDGE_FALLING:
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+	case IRQ_TYPE_LEVEL_LOW:
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 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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 		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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 			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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@@ -291,6 +293,8 @@
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 	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
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 	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
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 	{ .compatible = "fsl,pq3-gpio",     },
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+	{ .compatible = "fsl,ls1028a-gpio", },
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+	{ .compatible = "fsl,ls1088a-gpio", },
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 	{ .compatible = "fsl,qoriq-gpio",   },
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 	{}
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 };
..
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@@ -359,7 +363,19 @@
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 	gc->to_irq = mpc8xxx_gpio_to_irq;
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-	ret = gpiochip_add_data(gc, mpc8xxx_gc);
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+	/*
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+	 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
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+	 * the input enable of each individual GPIO port.  When an individual
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+	 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
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+	 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
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+	 * the port value to the GPIO Data Register.
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+	 */
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+	if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
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+	    of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
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+	    of_device_is_compatible(np, "fsl,ls1088a-gpio"))
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+		gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
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+
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+	ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
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 	if (ret) {
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 		pr_err("%pOF: GPIO chip registration failed with status %d\n",
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 		       np, ret);
..
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@@ -379,10 +395,20 @@
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 	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
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 	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
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-	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
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-					 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
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+	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
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+			       mpc8xxx_gpio_irq_cascade,
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+			       IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
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+			       mpc8xxx_gc);
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+	if (ret) {
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+		dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
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+			np->full_name, mpc8xxx_gc->irqn, ret);
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+		goto err;
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+	}
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+
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 	return 0;
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 err:
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+	if (mpc8xxx_gc->irq)
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+		irq_domain_remove(mpc8xxx_gc->irq);
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 	iounmap(mpc8xxx_gc->regs);
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 	return ret;
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 }
..
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@@ -396,7 +422,6 @@
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 		irq_domain_remove(mpc8xxx_gc->irq);
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 	}
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-	gpiochip_remove(&mpc8xxx_gc->gc);
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 	iounmap(mpc8xxx_gc->regs);
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 	return 0;