write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/gpio/gpio-dwapb.c
..
..
@@ -1,9 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * Copyright (c) 2011 Jamie Iles
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
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4
  *
8
5
  * All enquiries to support@picochip.com
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6
  */
..
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@@ -16,7 +13,6 @@
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13
 #include <linux/io.h>
17
14
 #include <linux/ioport.h>
18
15
 #include <linux/irq.h>
19
-#include <linux/irqdomain.h>
20
16
 #include <linux/module.h>
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17
 #include <linux/of.h>
22
18
 #include <linux/of_address.h>
..
..
@@ -30,6 +26,7 @@
30
26
 #include <linux/slab.h>
31
27
 
32
28
 #include "gpiolib.h"
29
+#include "gpiolib-acpi.h"
33
30
 
34
31
 #define GPIO_SWPORTA_DR		0x00
35
32
 #define GPIO_SWPORTA_DDR	0x04
..
..
@@ -66,6 +63,8 @@
66
63
 #define GPIO_INTSTATUS_V2	0x3c
67
64
 #define GPIO_PORTA_EOI_V2	0x40
68
65
 
66
+#define DWAPB_NR_CLOCKS		2
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+
69
68
 struct dwapb_gpio;
70
69
 
71
70
 #ifdef CONFIG_PM_SLEEP
..
..
@@ -83,25 +82,32 @@
83
82
 };
84
83
 #endif
85
84
 
85
+struct dwapb_gpio_port_irqchip {
86
+	struct irq_chip		irqchip;
87
+	unsigned int		nr_irqs;
88
+	unsigned int		irq[DWAPB_MAX_GPIOS];
89
+};
90
+
86
91
 struct dwapb_gpio_port {
87
92
 	struct gpio_chip	gc;
88
-	bool			is_registered;
93
+	struct dwapb_gpio_port_irqchip *pirq;
89
94
 	struct dwapb_gpio	*gpio;
90
95
 #ifdef CONFIG_PM_SLEEP
91
96
 	struct dwapb_context	*ctx;
92
97
 #endif
93
98
 	unsigned int		idx;
94
99
 };
100
+#define to_dwapb_gpio(_gc) \
101
+	(container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
95
102
 
96
103
 struct dwapb_gpio {
97
104
 	struct	device		*dev;
98
105
 	void __iomem		*regs;
99
106
 	struct dwapb_gpio_port	*ports;
100
107
 	unsigned int		nr_ports;
101
-	struct irq_domain	*domain;
102
108
 	unsigned int		flags;
103
109
 	struct reset_control	*rst;
104
-	struct clk		*clk;
110
+	struct clk_bulk_data	clks[DWAPB_NR_CLOCKS];
105
111
 };
106
112
 
107
113
 static inline u32 gpio_reg_v2_convert(unsigned int offset)
..
..
@@ -147,14 +153,6 @@
147
153
 	gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
148
154
 }
149
155
 
150
-static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
151
-{
152
-	struct dwapb_gpio_port *port = gpiochip_get_data(gc);
153
-	struct dwapb_gpio *gpio = port->gpio;
154
-
155
-	return irq_find_mapping(gpio->domain, offset);
156
-}
157
-
158
156
 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
159
157
 {
160
158
 	struct dwapb_gpio_port *port;
..
..
@@ -162,7 +160,7 @@
162
160
 
163
161
 	for (i = 0; i < gpio->nr_ports; i++) {
164
162
 		port = &gpio->ports[i];
165
-		if (port->idx == offs / 32)
163
+		if (port->idx == offs / DWAPB_MAX_GPIOS)
166
164
 			return port;
167
165
 	}
168
166
 
..
..
@@ -182,7 +180,7 @@
182
180
 
183
181
 	pol = dwapb_read(gpio, GPIO_INT_POLARITY);
184
182
 	/* Just read the current value right out of the data register */
185
-	val = gc->get(gc, offs % 32);
183
+	val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
186
184
 	if (val)
187
185
 		pol &= ~BIT(offs);
188
186
 	else
..
..
@@ -193,22 +191,22 @@
193
191
 
194
192
 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
195
193
 {
196
-	u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
197
-	u32 ret = irq_status;
194
+	struct gpio_chip *gc = &gpio->ports[0].gc;
195
+	unsigned long irq_status;
196
+	irq_hw_number_t hwirq;
198
197
 
199
-	while (irq_status) {
200
-		int hwirq = fls(irq_status) - 1;
201
-		int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
198
+	irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
199
+	for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
200
+		int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
201
+		u32 irq_type = irq_get_trigger_type(gpio_irq);
202
202
 
203
203
 		generic_handle_irq(gpio_irq);
204
-		irq_status &= ~BIT(hwirq);
205
204
 
206
-		if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
207
-			== IRQ_TYPE_EDGE_BOTH)
205
+		if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
208
206
 			dwapb_toggle_trigger(gpio, hwirq);
209
207
 	}
210
208
 
211
-	return ret;
209
+	return irq_status;
212
210
 }
213
211
 
214
212
 static void dwapb_irq_handler(struct irq_desc *desc)
..
..
@@ -216,77 +214,90 @@
216
214
 	struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
217
215
 	struct irq_chip *chip = irq_desc_get_chip(desc);
218
216
 
217
+	chained_irq_enter(chip, desc);
219
218
 	dwapb_do_irq(gpio);
219
+	chained_irq_exit(chip, desc);
220
+}
220
221
 
221
-	if (chip->irq_eoi)
222
-		chip->irq_eoi(irq_desc_get_irq_data(desc));
222
+static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
223
+{
224
+	return IRQ_RETVAL(dwapb_do_irq(dev_id));
225
+}
226
+
227
+static void dwapb_irq_ack(struct irq_data *d)
228
+{
229
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
230
+	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
231
+	u32 val = BIT(irqd_to_hwirq(d));
232
+	unsigned long flags;
233
+
234
+	spin_lock_irqsave(&gc->bgpio_lock, flags);
235
+	dwapb_write(gpio, GPIO_PORTA_EOI, val);
236
+	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
237
+}
238
+
239
+static void dwapb_irq_mask(struct irq_data *d)
240
+{
241
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242
+	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
243
+	unsigned long flags;
244
+	u32 val;
245
+
246
+	spin_lock_irqsave(&gc->bgpio_lock, flags);
247
+	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
248
+	dwapb_write(gpio, GPIO_INTMASK, val);
249
+	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
250
+}
251
+
252
+static void dwapb_irq_unmask(struct irq_data *d)
253
+{
254
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
255
+	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
256
+	unsigned long flags;
257
+	u32 val;
258
+
259
+	spin_lock_irqsave(&gc->bgpio_lock, flags);
260
+	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
261
+	dwapb_write(gpio, GPIO_INTMASK, val);
262
+	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
223
263
 }
224
264
 
225
265
 static void dwapb_irq_enable(struct irq_data *d)
226
266
 {
227
-	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
228
-	struct dwapb_gpio *gpio = igc->private;
229
-	struct gpio_chip *gc = &gpio->ports[0].gc;
267
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
268
+	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
230
269
 	unsigned long flags;
231
270
 	u32 val;
232
271
 
233
272
 	spin_lock_irqsave(&gc->bgpio_lock, flags);
234
273
 	val = dwapb_read(gpio, GPIO_INTEN);
235
-	val |= BIT(d->hwirq);
274
+	val |= BIT(irqd_to_hwirq(d));
236
275
 	dwapb_write(gpio, GPIO_INTEN, val);
237
276
 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
238
277
 }
239
278
 
240
279
 static void dwapb_irq_disable(struct irq_data *d)
241
280
 {
242
-	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
243
-	struct dwapb_gpio *gpio = igc->private;
244
-	struct gpio_chip *gc = &gpio->ports[0].gc;
281
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
282
+	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
245
283
 	unsigned long flags;
246
284
 	u32 val;
247
285
 
248
286
 	spin_lock_irqsave(&gc->bgpio_lock, flags);
249
287
 	val = dwapb_read(gpio, GPIO_INTEN);
250
-	val &= ~BIT(d->hwirq);
288
+	val &= ~BIT(irqd_to_hwirq(d));
251
289
 	dwapb_write(gpio, GPIO_INTEN, val);
252
290
 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
253
291
 }
254
292
 
255
-static int dwapb_irq_reqres(struct irq_data *d)
256
-{
257
-	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
258
-	struct dwapb_gpio *gpio = igc->private;
259
-	struct gpio_chip *gc = &gpio->ports[0].gc;
260
-	int ret;
261
-
262
-	ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d));
263
-	if (ret) {
264
-		dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
265
-			irqd_to_hwirq(d));
266
-		return ret;
267
-	}
268
-	return 0;
269
-}
270
-
271
-static void dwapb_irq_relres(struct irq_data *d)
272
-{
273
-	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
274
-	struct dwapb_gpio *gpio = igc->private;
275
-	struct gpio_chip *gc = &gpio->ports[0].gc;
276
-
277
-	gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
278
-}
279
-
280
293
 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
281
294
 {
282
-	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
283
-	struct dwapb_gpio *gpio = igc->private;
284
-	struct gpio_chip *gc = &gpio->ports[0].gc;
285
-	int bit = d->hwirq;
295
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
296
+	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
297
+	irq_hw_number_t bit = irqd_to_hwirq(d);
286
298
 	unsigned long level, polarity, flags;
287
299
 
288
-	if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
289
-		     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
300
+	if (type & ~IRQ_TYPE_SENSE_MASK)
290
301
 		return -EINVAL;
291
302
 
292
303
 	spin_lock_irqsave(&gc->bgpio_lock, flags);
..
..
@@ -316,7 +327,10 @@
316
327
 		break;
317
328
 	}
318
329
 
319
-	irq_setup_alt_chip(d, type);
330
+	if (type & IRQ_TYPE_LEVEL_MASK)
331
+		irq_set_handler_locked(d, handle_level_irq);
332
+	else if (type & IRQ_TYPE_EDGE_BOTH)
333
+		irq_set_handler_locked(d, handle_edge_irq);
320
334
 
321
335
 	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
322
336
 	if (type != IRQ_TYPE_EDGE_BOTH)
..
..
@@ -329,14 +343,15 @@
329
343
 #ifdef CONFIG_PM_SLEEP
330
344
 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
331
345
 {
332
-	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
333
-	struct dwapb_gpio *gpio = igc->private;
346
+	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
347
+	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
334
348
 	struct dwapb_context *ctx = gpio->ports[0].ctx;
349
+	irq_hw_number_t bit = irqd_to_hwirq(d);
335
350
 
336
351
 	if (enable)
337
-		ctx->wake_en |= BIT(d->hwirq);
352
+		ctx->wake_en |= BIT(bit);
338
353
 	else
339
-		ctx->wake_en &= ~BIT(d->hwirq);
354
+		ctx->wake_en &= ~BIT(bit);
340
355
 
341
356
 	return 0;
342
357
 }
..
..
@@ -354,9 +369,10 @@
354
369
 
355
370
 	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
356
371
 	if (debounce)
357
-		dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
372
+		val_deb |= mask;
358
373
 	else
359
-		dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
374
+		val_deb &= ~mask;
375
+	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
360
376
 
361
377
 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
362
378
 
..
..
@@ -375,84 +391,67 @@
375
391
 	return dwapb_gpio_set_debounce(gc, offset, debounce);
376
392
 }
377
393
 
378
-static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
394
+static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
395
+			      struct dwapb_port_property *pp)
379
396
 {
380
-	u32 worked;
381
-	struct dwapb_gpio *gpio = dev_id;
397
+	int i;
382
398
 
383
-	worked = dwapb_do_irq(gpio);
399
+	/* Group all available IRQs into an array of parental IRQs. */
400
+	for (i = 0; i < pp->ngpio; ++i) {
401
+		if (!pp->irq[i])
402
+			continue;
384
403
 
385
-	return worked ? IRQ_HANDLED : IRQ_NONE;
404
+		pirq->irq[pirq->nr_irqs++] = pp->irq[i];
405
+	}
406
+
407
+	return pirq->nr_irqs ? 0 : -ENOENT;
386
408
 }
387
409
 
388
410
 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
389
411
 				 struct dwapb_gpio_port *port,
390
412
 				 struct dwapb_port_property *pp)
391
413
 {
414
+	struct dwapb_gpio_port_irqchip *pirq;
392
415
 	struct gpio_chip *gc = &port->gc;
393
-	struct fwnode_handle  *fwnode = pp->fwnode;
394
-	struct irq_chip_generic	*irq_gc = NULL;
395
-	unsigned int hwirq, ngpio = gc->ngpio;
396
-	struct irq_chip_type *ct;
397
-	int err, i;
416
+	struct gpio_irq_chip *girq;
417
+	int err;
398
418
 
399
-	gpio->domain = irq_domain_create_linear(fwnode, ngpio,
400
-						 &irq_generic_chip_ops, gpio);
401
-	if (!gpio->domain)
419
+	pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
420
+	if (!pirq)
402
421
 		return;
403
422
 
404
-	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
405
-					     DWAPB_DRIVER_NAME, handle_level_irq,
406
-					     IRQ_NOREQUEST, 0,
407
-					     IRQ_GC_INIT_NESTED_LOCK);
408
-	if (err) {
409
-		dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
410
-		irq_domain_remove(gpio->domain);
411
-		gpio->domain = NULL;
412
-		return;
423
+	if (dwapb_convert_irqs(pirq, pp)) {
424
+		dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
425
+		goto err_kfree_pirq;
413
426
 	}
414
427
 
415
-	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
416
-	if (!irq_gc) {
417
-		irq_domain_remove(gpio->domain);
418
-		gpio->domain = NULL;
419
-		return;
420
-	}
428
+	girq = &gc->irq;
429
+	girq->handler = handle_bad_irq;
430
+	girq->default_type = IRQ_TYPE_NONE;
421
431
 
422
-	irq_gc->reg_base = gpio->regs;
423
-	irq_gc->private = gpio;
424
-
425
-	for (i = 0; i < 2; i++) {
426
-		ct = &irq_gc->chip_types[i];
427
-		ct->chip.irq_ack = irq_gc_ack_set_bit;
428
-		ct->chip.irq_mask = irq_gc_mask_set_bit;
429
-		ct->chip.irq_unmask = irq_gc_mask_clr_bit;
430
-		ct->chip.irq_set_type = dwapb_irq_set_type;
431
-		ct->chip.irq_enable = dwapb_irq_enable;
432
-		ct->chip.irq_disable = dwapb_irq_disable;
433
-		ct->chip.irq_request_resources = dwapb_irq_reqres;
434
-		ct->chip.irq_release_resources = dwapb_irq_relres;
432
+	port->pirq = pirq;
433
+	pirq->irqchip.name = DWAPB_DRIVER_NAME;
434
+	pirq->irqchip.irq_ack = dwapb_irq_ack;
435
+	pirq->irqchip.irq_mask = dwapb_irq_mask;
436
+	pirq->irqchip.irq_unmask = dwapb_irq_unmask;
437
+	pirq->irqchip.irq_set_type = dwapb_irq_set_type;
438
+	pirq->irqchip.irq_enable = dwapb_irq_enable;
439
+	pirq->irqchip.irq_disable = dwapb_irq_disable;
435
440
 #ifdef CONFIG_PM_SLEEP
436
-		ct->chip.irq_set_wake = dwapb_irq_set_wake;
441
+	pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
437
442
 #endif
438
-		ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
439
-		ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
440
-		ct->type = IRQ_TYPE_LEVEL_MASK;
441
-	}
442
-
443
-	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
444
-	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
445
-	irq_gc->chip_types[1].handler = handle_edge_irq;
446
443
 
447
444
 	if (!pp->irq_shared) {
448
-		int i;
449
-
450
-		for (i = 0; i < pp->ngpio; i++) {
451
-			if (pp->irq[i] >= 0)
452
-				irq_set_chained_handler_and_data(pp->irq[i],
453
-						dwapb_irq_handler, gpio);
454
-		}
445
+		girq->num_parents = pirq->nr_irqs;
446
+		girq->parents = pirq->irq;
447
+		girq->parent_handler_data = gpio;
448
+		girq->parent_handler = dwapb_irq_handler;
455
449
 	} else {
450
+		/* This will let us handle the parent IRQ in the driver */
451
+		girq->num_parents = 0;
452
+		girq->parents = NULL;
453
+		girq->parent_handler = NULL;
454
+
456
455
 		/*
457
456
 		 * Request a shared IRQ since where MFD would have devices
458
457
 		 * using the same irq pin
..
..
@@ -462,33 +461,16 @@
462
461
 				       IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
463
462
 		if (err) {
464
463
 			dev_err(gpio->dev, "error requesting IRQ\n");
465
-			irq_domain_remove(gpio->domain);
466
-			gpio->domain = NULL;
467
-			return;
464
+			goto err_kfree_pirq;
468
465
 		}
469
466
 	}
470
467
 
471
-	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
472
-		irq_create_mapping(gpio->domain, hwirq);
468
+	girq->chip = &pirq->irqchip;
473
469
 
474
-	port->gc.to_irq = dwapb_gpio_to_irq;
475
-}
470
+	return;
476
471
 
477
-static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
478
-{
479
-	struct dwapb_gpio_port *port = &gpio->ports[0];
480
-	struct gpio_chip *gc = &port->gc;
481
-	unsigned int ngpio = gc->ngpio;
482
-	irq_hw_number_t hwirq;
483
-
484
-	if (!gpio->domain)
485
-		return;
486
-
487
-	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
488
-		irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
489
-
490
-	irq_domain_remove(gpio->domain);
491
-	gpio->domain = NULL;
472
+err_kfree_pirq:
473
+	devm_kfree(gpio->dev, pirq);
492
474
 }
493
475
 
494
476
 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
..
..
@@ -509,10 +491,9 @@
509
491
 		return -ENOMEM;
510
492
 #endif
511
493
 
512
-	dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE);
513
-	set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE);
514
-	dirout = gpio->regs + GPIO_SWPORTA_DDR +
515
-		(pp->idx * GPIO_SWPORT_DDR_STRIDE);
494
+	dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
495
+	set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
496
+	dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
516
497
 
517
498
 	/* This registers 32 GPIO lines per port */
518
499
 	err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
..
..
@@ -533,47 +514,46 @@
533
514
 	if (pp->idx == 0)
534
515
 		port->gc.set_config = dwapb_gpio_set_config;
535
516
 
536
-	if (pp->has_irq)
517
+	/* Only port A can provide interrupts in all configurations of the IP */
518
+	if (pp->idx == 0)
537
519
 		dwapb_configure_irqs(gpio, port, pp);
538
520
 
539
-	err = gpiochip_add_data(&port->gc, port);
521
+	err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
540
522
 	if (err) {
541
523
 		dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
542
524
 			port->idx);
543
525
 		return err;
544
526
 	}
545
527
 
546
-	/* Add GPIO-signaled ACPI event support */
547
-	acpi_gpiochip_request_interrupts(&port->gc);
548
-
549
-	port->is_registered = true;
550
-
551
528
 	return 0;
552
529
 }
553
530
 
554
-static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
531
+static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
532
+			  struct dwapb_port_property *pp)
555
533
 {
556
-	unsigned int m;
534
+	struct device_node *np = NULL;
535
+	int irq = -ENXIO, j;
557
536
 
558
-	for (m = 0; m < gpio->nr_ports; ++m) {
559
-		struct dwapb_gpio_port *port = &gpio->ports[m];
537
+	if (fwnode_property_read_bool(fwnode, "interrupt-controller"))
538
+		np = to_of_node(fwnode);
560
539
 
561
-		if (!port->is_registered)
562
-			continue;
563
-
564
-		acpi_gpiochip_free_interrupts(&port->gc);
565
-		gpiochip_remove(&port->gc);
540
+	for (j = 0; j < pp->ngpio; j++) {
541
+		if (np)
542
+			irq = of_irq_get(np, j);
543
+		else if (has_acpi_companion(dev))
544
+			irq = platform_get_irq_optional(to_platform_device(dev), j);
545
+		if (irq > 0)
546
+			pp->irq[j] = irq;
566
547
 	}
567
548
 }
568
549
 
569
-static struct dwapb_platform_data *
570
-dwapb_gpio_get_pdata(struct device *dev)
550
+static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
571
551
 {
572
552
 	struct fwnode_handle *fwnode;
573
553
 	struct dwapb_platform_data *pdata;
574
554
 	struct dwapb_port_property *pp;
575
555
 	int nports;
576
-	int i, j;
556
+	int i;
577
557
 
578
558
 	nports = device_get_child_node_count(dev);
579
559
 	if (nports == 0)
..
..
@@ -591,8 +571,6 @@
591
571
 
592
572
 	i = 0;
593
573
 	device_for_each_child_node(dev, fwnode)  {
594
-		struct device_node *np = NULL;
595
-
596
574
 		pp = &pdata->properties[i++];
597
575
 		pp->fwnode = fwnode;
598
576
 
..
..
@@ -604,12 +582,12 @@
604
582
 			return ERR_PTR(-EINVAL);
605
583
 		}
606
584
 
607
-		if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
608
-					 &pp->ngpio)) {
585
+		if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
586
+		    fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
609
587
 			dev_info(dev,
610
588
 				 "failed to get number of gpios for port%d\n",
611
589
 				 i);
612
-			pp->ngpio = 32;
590
+			pp->ngpio = DWAPB_MAX_GPIOS;
613
591
 		}
614
592
 
615
593
 		pp->irq_shared	= false;
..
..
@@ -619,31 +597,66 @@
619
597
 		 * Only port A can provide interrupts in all configurations of
620
598
 		 * the IP.
621
599
 		 */
622
-		if (pp->idx != 0)
623
-			continue;
624
-
625
-		if (dev->of_node && fwnode_property_read_bool(fwnode,
626
-						  "interrupt-controller")) {
627
-			np = to_of_node(fwnode);
628
-		}
629
-
630
-		for (j = 0; j < pp->ngpio; j++) {
631
-			pp->irq[j] = -ENXIO;
632
-
633
-			if (np)
634
-				pp->irq[j] = of_irq_get(np, j);
635
-			else if (has_acpi_companion(dev))
636
-				pp->irq[j] = platform_get_irq(to_platform_device(dev), j);
637
-
638
-			if (pp->irq[j] >= 0)
639
-				pp->has_irq = true;
640
-		}
641
-
642
-		if (!pp->has_irq)
643
-			dev_warn(dev, "no irq for port%d\n", pp->idx);
600
+		if (pp->idx == 0)
601
+			dwapb_get_irq(dev, fwnode, pp);
644
602
 	}
645
603
 
646
604
 	return pdata;
605
+}
606
+
607
+static void dwapb_assert_reset(void *data)
608
+{
609
+	struct dwapb_gpio *gpio = data;
610
+
611
+	reset_control_assert(gpio->rst);
612
+}
613
+
614
+static int dwapb_get_reset(struct dwapb_gpio *gpio)
615
+{
616
+	int err;
617
+
618
+	gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
619
+	if (IS_ERR(gpio->rst)) {
620
+		dev_err(gpio->dev, "Cannot get reset descriptor\n");
621
+		return PTR_ERR(gpio->rst);
622
+	}
623
+
624
+	err = reset_control_deassert(gpio->rst);
625
+	if (err) {
626
+		dev_err(gpio->dev, "Cannot deassert reset lane\n");
627
+		return err;
628
+	}
629
+
630
+	return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
631
+}
632
+
633
+static void dwapb_disable_clks(void *data)
634
+{
635
+	struct dwapb_gpio *gpio = data;
636
+
637
+	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
638
+}
639
+
640
+static int dwapb_get_clks(struct dwapb_gpio *gpio)
641
+{
642
+	int err;
643
+
644
+	/* Optional bus and debounce clocks */
645
+	gpio->clks[0].id = "bus";
646
+	gpio->clks[1].id = "db";
647
+	err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
648
+					 gpio->clks);
649
+	if (err)
650
+		return dev_err_probe(gpio->dev, err,
651
+				     "Cannot get APB/Debounce clocks\n");
652
+
653
+	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
654
+	if (err) {
655
+		dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
656
+		return err;
657
+	}
658
+
659
+	return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
647
660
 }
648
661
 
649
662
 static const struct of_device_id dwapb_of_match[] = {
..
..
@@ -664,7 +677,6 @@
664
677
 static int dwapb_gpio_probe(struct platform_device *pdev)
665
678
 {
666
679
 	unsigned int i;
667
-	struct resource *res;
668
680
 	struct dwapb_gpio *gpio;
669
681
 	int err;
670
682
 	struct device *dev = &pdev->dev;
..
..
@@ -686,70 +698,32 @@
686
698
 	gpio->dev = &pdev->dev;
687
699
 	gpio->nr_ports = pdata->nports;
688
700
 
689
-	gpio->rst = devm_reset_control_get_optional_shared(dev, NULL);
690
-	if (IS_ERR(gpio->rst))
691
-		return PTR_ERR(gpio->rst);
692
-
693
-	reset_control_deassert(gpio->rst);
701
+	err = dwapb_get_reset(gpio);
702
+	if (err)
703
+		return err;
694
704
 
695
705
 	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
696
706
 				   sizeof(*gpio->ports), GFP_KERNEL);
697
707
 	if (!gpio->ports)
698
708
 		return -ENOMEM;
699
709
 
700
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701
-	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
710
+	gpio->regs = devm_platform_ioremap_resource(pdev, 0);
702
711
 	if (IS_ERR(gpio->regs))
703
712
 		return PTR_ERR(gpio->regs);
704
713
 
705
-	/* Optional bus clock */
706
-	gpio->clk = devm_clk_get(&pdev->dev, "bus");
707
-	if (!IS_ERR(gpio->clk)) {
708
-		err = clk_prepare_enable(gpio->clk);
709
-		if (err) {
710
-			dev_info(&pdev->dev, "Cannot enable clock\n");
711
-			return err;
712
-		}
713
-	}
714
+	err = dwapb_get_clks(gpio);
715
+	if (err)
716
+		return err;
714
717
 
715
-	gpio->flags = 0;
716
-	if (dev->of_node) {
717
-		gpio->flags = (uintptr_t)of_device_get_match_data(dev);
718
-	} else if (has_acpi_companion(dev)) {
719
-		const struct acpi_device_id *acpi_id;
720
-
721
-		acpi_id = acpi_match_device(dwapb_acpi_match, dev);
722
-		if (acpi_id) {
723
-			if (acpi_id->driver_data)
724
-				gpio->flags = acpi_id->driver_data;
725
-		}
726
-	}
718
+	gpio->flags = (uintptr_t)device_get_match_data(dev);
727
719
 
728
720
 	for (i = 0; i < gpio->nr_ports; i++) {
729
721
 		err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
730
722
 		if (err)
731
-			goto out_unregister;
723
+			return err;
732
724
 	}
725
+
733
726
 	platform_set_drvdata(pdev, gpio);
734
-
735
-	return 0;
736
-
737
-out_unregister:
738
-	dwapb_gpio_unregister(gpio);
739
-	dwapb_irq_teardown(gpio);
740
-	clk_disable_unprepare(gpio->clk);
741
-
742
-	return err;
743
-}
744
-
745
-static int dwapb_gpio_remove(struct platform_device *pdev)
746
-{
747
-	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
748
-
749
-	dwapb_gpio_unregister(gpio);
750
-	dwapb_irq_teardown(gpio);
751
-	reset_control_assert(gpio->rst);
752
-	clk_disable_unprepare(gpio->clk);
753
727
 
754
728
 	return 0;
755
729
 }
..
..
@@ -757,8 +731,7 @@
757
731
 #ifdef CONFIG_PM_SLEEP
758
732
 static int dwapb_gpio_suspend(struct device *dev)
759
733
 {
760
-	struct platform_device *pdev = to_platform_device(dev);
761
-	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
734
+	struct dwapb_gpio *gpio = dev_get_drvdata(dev);
762
735
 	struct gpio_chip *gc	= &gpio->ports[0].gc;
763
736
 	unsigned long flags;
764
737
 	int i;
..
..
@@ -768,8 +741,6 @@
768
741
 		unsigned int offset;
769
742
 		unsigned int idx = gpio->ports[i].idx;
770
743
 		struct dwapb_context *ctx = gpio->ports[i].ctx;
771
-
772
-		BUG_ON(!ctx);
773
744
 
774
745
 		offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
775
746
 		ctx->dir = dwapb_read(gpio, offset);
..
..
@@ -789,35 +760,34 @@
789
760
 			ctx->int_deb	= dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
790
761
 
791
762
 			/* Mask out interrupts */
792
-			dwapb_write(gpio, GPIO_INTMASK,
793
-				    0xffffffff & ~ctx->wake_en);
763
+			dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
794
764
 		}
795
765
 	}
796
766
 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
797
767
 
798
-	clk_disable_unprepare(gpio->clk);
768
+	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
799
769
 
800
770
 	return 0;
801
771
 }
802
772
 
803
773
 static int dwapb_gpio_resume(struct device *dev)
804
774
 {
805
-	struct platform_device *pdev = to_platform_device(dev);
806
-	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
775
+	struct dwapb_gpio *gpio = dev_get_drvdata(dev);
807
776
 	struct gpio_chip *gc	= &gpio->ports[0].gc;
808
777
 	unsigned long flags;
809
-	int i;
778
+	int i, err;
810
779
 
811
-	if (!IS_ERR(gpio->clk))
812
-		clk_prepare_enable(gpio->clk);
780
+	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
781
+	if (err) {
782
+		dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
783
+		return err;
784
+	}
813
785
 
814
786
 	spin_lock_irqsave(&gc->bgpio_lock, flags);
815
787
 	for (i = 0; i < gpio->nr_ports; i++) {
816
788
 		unsigned int offset;
817
789
 		unsigned int idx = gpio->ports[i].idx;
818
790
 		struct dwapb_context *ctx = gpio->ports[i].ctx;
819
-
820
-		BUG_ON(!ctx);
821
791
 
822
792
 		offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
823
793
 		dwapb_write(gpio, offset, ctx->data);
..
..
@@ -853,11 +823,10 @@
853
823
 	.driver		= {
854
824
 		.name	= DWAPB_DRIVER_NAME,
855
825
 		.pm	= &dwapb_gpio_pm_ops,
856
-		.of_match_table = of_match_ptr(dwapb_of_match),
857
-		.acpi_match_table = ACPI_PTR(dwapb_acpi_match),
826
+		.of_match_table = dwapb_of_match,
827
+		.acpi_match_table = dwapb_acpi_match,
858
828
 	},
859
829
 	.probe		= dwapb_gpio_probe,
860
-	.remove		= dwapb_gpio_remove,
861
830
 };
862
831
 
863
832
 module_platform_driver(dwapb_gpio_driver);