| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * FSI hub master driver |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) IBM Corporation 2016 |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License version 2 as |
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| 8 | | - * published by the Free Software Foundation. |
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| 9 | | - * |
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| 10 | | - * This program is distributed in the hope that it will be useful, |
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| 11 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 13 | | - * GNU General Public License for more details. |
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| 14 | 6 | */ |
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| 15 | 7 | |
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| 16 | 8 | #include <linux/delay.h> |
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| .. | .. |
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| 21 | 13 | |
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| 22 | 14 | #include "fsi-master.h" |
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| 23 | 15 | |
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| 24 | | -/* Control Registers */ |
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| 25 | | -#define FSI_MMODE 0x0 /* R/W: mode */ |
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| 26 | | -#define FSI_MDLYR 0x4 /* R/W: delay */ |
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| 27 | | -#define FSI_MCRSP 0x8 /* R/W: clock rate */ |
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| 28 | | -#define FSI_MENP0 0x10 /* R/W: enable */ |
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| 29 | | -#define FSI_MLEVP0 0x18 /* R: plug detect */ |
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| 30 | | -#define FSI_MSENP0 0x18 /* S: Set enable */ |
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| 31 | | -#define FSI_MCENP0 0x20 /* C: Clear enable */ |
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| 32 | | -#define FSI_MAEB 0x70 /* R: Error address */ |
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| 33 | | -#define FSI_MVER 0x74 /* R: master version/type */ |
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| 34 | | -#define FSI_MRESP0 0xd0 /* W: Port reset */ |
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| 35 | | -#define FSI_MESRB0 0x1d0 /* R: Master error status */ |
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| 36 | | -#define FSI_MRESB0 0x1d0 /* W: Reset bridge */ |
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| 37 | | -#define FSI_MECTRL 0x2e0 /* W: Error control */ |
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| 38 | | - |
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| 39 | | -/* MMODE: Mode control */ |
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| 40 | | -#define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */ |
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| 41 | | -#define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */ |
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| 42 | | -#define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */ |
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| 43 | | -#define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */ |
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| 44 | | - /* MSB=1, LSB=0 is 0.8 ms */ |
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| 45 | | - /* MSB=0, LSB=1 is 0.9 ms */ |
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| 46 | | -#define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */ |
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| 47 | | -#define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */ |
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| 48 | | -#define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */ |
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| 49 | | -#define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */ |
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| 50 | | - |
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| 51 | | -/* MRESB: Reset brindge */ |
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| 52 | | -#define FSI_MRESB_RST_GEN 0x80000000 /* General reset */ |
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| 53 | | -#define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */ |
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| 54 | | - |
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| 55 | | -/* MRESB: Reset port */ |
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| 56 | | -#define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */ |
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| 57 | | -#define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */ |
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| 58 | | -#define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */ |
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| 59 | | -#define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */ |
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| 60 | | -#define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */ |
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| 61 | | - |
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| 62 | | -/* MECTRL: Error control */ |
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| 63 | | -#define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */ |
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| 64 | | - /* master 0 in error */ |
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| 65 | | -#define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */ |
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| 66 | | - |
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| 67 | 16 | #define FSI_ENGID_HUB_MASTER 0x1c |
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| 68 | | -#define FSI_HUB_LINK_OFFSET 0x80000 |
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| 69 | | -#define FSI_HUB_LINK_SIZE 0x80000 |
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| 70 | | -#define FSI_HUB_MASTER_MAX_LINKS 8 |
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| 71 | 17 | |
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| 72 | 18 | #define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ |
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| 73 | 19 | |
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| .. | .. |
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| 131 | 77 | return hub_master_write(master, link, 0, addr, &cmd, sizeof(cmd)); |
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| 132 | 78 | } |
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| 133 | 79 | |
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| 134 | | -static int hub_master_link_enable(struct fsi_master *master, int link) |
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| 80 | +static int hub_master_link_enable(struct fsi_master *master, int link, |
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| 81 | + bool enable) |
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| 135 | 82 | { |
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| 136 | 83 | struct fsi_master_hub *hub = to_fsi_master_hub(master); |
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| 137 | 84 | int idx, bit; |
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| .. | .. |
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| 143 | 90 | |
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| 144 | 91 | reg = cpu_to_be32(0x80000000 >> bit); |
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| 145 | 92 | |
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| 93 | + if (!enable) |
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| 94 | + return fsi_device_write(hub->upstream, FSI_MCENP0 + (4 * idx), |
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| 95 | + ®, 4); |
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| 96 | + |
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| 146 | 97 | rc = fsi_device_write(hub->upstream, FSI_MSENP0 + (4 * idx), ®, 4); |
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| 98 | + if (rc) |
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| 99 | + return rc; |
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| 147 | 100 | |
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| 148 | 101 | mdelay(FSI_LINK_ENABLE_SETUP_TIME); |
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| 149 | 102 | |
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| 150 | | - fsi_device_read(hub->upstream, FSI_MENP0 + (4 * idx), ®, 4); |
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| 151 | | - |
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| 152 | | - return rc; |
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| 103 | + return 0; |
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| 153 | 104 | } |
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| 154 | 105 | |
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| 155 | 106 | static void hub_master_release(struct device *dev) |
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| .. | .. |
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| 325 | 276 | return 0; |
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| 326 | 277 | } |
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| 327 | 278 | |
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| 328 | | -static struct fsi_device_id hub_master_ids[] = { |
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| 279 | +static const struct fsi_device_id hub_master_ids[] = { |
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| 329 | 280 | { |
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| 330 | 281 | .engine_type = FSI_ENGID_HUB_MASTER, |
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| 331 | 282 | .version = FSI_VERSION_ANY, |
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