write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/edac/i7300_edac.c
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@@ -1,13 +1,11 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Intel 7300 class Memory Controllers kernel module (Clarksboro)
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- *
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- * This file may be distributed under the terms of the
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- * GNU General Public License version 2 only.
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  *
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  * Copyright (c) 2010 by:
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  *	 Mauro Carvalho Chehab
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  *
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- * Red Hat Inc. http://www.redhat.com
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+ * Red Hat Inc. https://www.redhat.com
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  *
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  * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
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  *	http://www.intel.com/Assets/PDF/datasheet/318082.pdf
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@@ -582,7 +580,7 @@
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  * @ch: Channel number within the branch (0 or 1)
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  * @branch: Branch number (0 or 1)
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  * @dinfo: Pointer to DIMM info where dimm size is stored
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- * @p_csrow: Pointer to the struct csrow_info that corresponds to that element
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+ * @dimm: Pointer to the struct dimm_info that corresponds to that element
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  */
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 static int decode_mtr(struct i7300_pvt *pvt,
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 		      int slot, int ch, int branch,
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@@ -796,8 +794,7 @@
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 			for (ch = 0; ch < max_channel; ch++) {
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 				int channel = to_channel(ch, branch);
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-				dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
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-					       mci->n_layers, branch, ch, slot);
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+				dimm = edac_get_dimm(mci, branch, ch, slot);
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 				dinfo = &pvt->dimm_info[slot][channel];
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@@ -819,7 +816,7 @@
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 /**
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  * decode_mir() - Decodes Memory Interleave Register (MIR) info
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- * @int mir_no: number of the MIR register to decode
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+ * @mir_no: number of the MIR register to decode
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  * @mir: array with the MIR data cached on the driver
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  */
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 static void decode_mir(int mir_no, u16 mir[MAX_MIR])
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@@ -1209,7 +1206,7 @@
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 MODULE_LICENSE("GPL");
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 MODULE_AUTHOR("Mauro Carvalho Chehab");
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-MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
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+MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");
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 MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
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 		   I7300_REVISION);
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