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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/clk/samsung/clk-exynos5250.c
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@@ -1,20 +1,17 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
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  * Copyright (c) 2013 Linaro Ltd.
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  * Author: Thomas Abraham <thomas.ab@samsung.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Common Clock Framework support for Exynos5250 SoC.
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 */
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 #include <dt-bindings/clock/exynos5250.h>
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 #include <linux/clk-provider.h>
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+#include <linux/io.h>
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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-#include <linux/syscore_ops.h>
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 #include "clk.h"
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 #include "clk-cpu.h"
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@@ -111,9 +108,6 @@
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 static void __iomem *reg_base;
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-#ifdef CONFIG_PM_SLEEP
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-static struct samsung_clk_reg_dump *exynos5250_save;
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-
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 /*
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  * list of controller registers to be saved and restored during a
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  * suspend/resume cycle.
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@@ -171,41 +165,6 @@
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 	GATE_IP_ISP0,
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 	GATE_IP_ISP1,
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 };
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-
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-static int exynos5250_clk_suspend(void)
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-{
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-	samsung_clk_save(reg_base, exynos5250_save,
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-				ARRAY_SIZE(exynos5250_clk_regs));
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-
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-	return 0;
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-}
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-
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-static void exynos5250_clk_resume(void)
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-{
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-	samsung_clk_restore(reg_base, exynos5250_save,
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-				ARRAY_SIZE(exynos5250_clk_regs));
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-}
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-
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-static struct syscore_ops exynos5250_clk_syscore_ops = {
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-	.suspend = exynos5250_clk_suspend,
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-	.resume = exynos5250_clk_resume,
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-};
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-
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-static void __init exynos5250_clk_sleep_init(void)
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-{
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-	exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
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-					ARRAY_SIZE(exynos5250_clk_regs));
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-	if (!exynos5250_save) {
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-		pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
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-			__func__);
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-		return;
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-	}
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-
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-	register_syscore_ops(&exynos5250_clk_syscore_ops);
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-}
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-#else
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-static void __init exynos5250_clk_sleep_init(void) {}
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-#endif
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 /* list of all parent clock list */
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 PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };
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@@ -294,14 +253,14 @@
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 	/*
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 	 * CMU_CPU
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 	 */
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-	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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+	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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 					CLK_SET_RATE_PARENT, 0),
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 	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
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 	/*
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 	 * CMU_CORE
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 	 */
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-	MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
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+	MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
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 	/*
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 	 * CMU_TOP
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@@ -722,6 +681,10 @@
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 	.pd_name	= "DISP1",
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 };
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+static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
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+	&exynos5250_disp_subcmu,
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+};
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+
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 static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
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 	/* sorted in descending order */
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 	/* PLL_36XX_RATE(rate, m, p, s, k) */
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@@ -819,6 +782,7 @@
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 {
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 	struct samsung_clk_provider *ctx;
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 	unsigned int tmp;
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+	struct clk_hw **hws;
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 	if (np) {
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 		reg_base = of_iomap(np, 0);
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@@ -829,6 +793,7 @@
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 	}
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 	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
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+	hws = ctx->clk_data.hws;
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 	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
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 			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
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@@ -858,7 +823,7 @@
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 	samsung_clk_register_gate(ctx, exynos5250_gate_clks,
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 			ARRAY_SIZE(exynos5250_gate_clks));
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 	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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-			mout_cpu_p[0], mout_cpu_p[1], 0x200,
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+			hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
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 			exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
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 			CLK_CPU_HAS_DIV1);
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@@ -882,8 +847,10 @@
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 		PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
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 	__raw_writel(tmp, reg_base + PWR_CTRL2);
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-	exynos5250_clk_sleep_init();
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-	exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
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+	samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
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+			       ARRAY_SIZE(exynos5250_clk_regs));
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+	exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
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+			     exynos5250_subcmus);
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 	samsung_clk_of_add_provider(np, ctx);
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