write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/clk/renesas/r8a7795-cpg-mssr.c
..
..
@@ -1,15 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
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  *
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  * Copyright (C) 2015 Glider bvba
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+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
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  *
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  * Based on clk-rcar-gen3.c
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  *
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  * Copyright (C) 2015 Renesas Electronics Corp.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; version 2 of the License.
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  */
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 #include <linux/device.h>
..
..
@@ -46,6 +44,7 @@
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 	CLK_S3,
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 	CLK_SDSRC,
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 	CLK_SSPSRC,
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+	CLK_RPCSRC,
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 	CLK_RINT,
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 	/* Module Clocks */
..
..
@@ -72,10 +71,18 @@
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 	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
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 	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
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 	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
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+	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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+
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+	DEF_BASE("rpc",		R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
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+		 CLK_RPCSRC),
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+	DEF_BASE("rpcd2",	R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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+		 R8A7795_CLK_RPC),
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+
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+	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
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 	/* Core Clock Outputs */
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-	DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
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-	DEF_BASE("z2",          R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
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+	DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
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+	DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),
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 	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
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 	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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 	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
..
..
@@ -105,14 +112,14 @@
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 	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
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 	DEF_FIXED("cr",         R8A7795_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
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 	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
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+	DEF_FIXED("cpex",       R8A7795_CLK_CPEX,  CLK_EXTAL,      2, 1),
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 	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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 	DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
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 	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
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 	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
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-	DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
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-	DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
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+	DEF_GEN3_OSC("osc",     R8A7795_CLK_OSC,   CLK_EXTAL,     8),
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 	DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
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 };
..
..
@@ -130,14 +137,15 @@
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 	DEF_MOD("msiof2",		 209,	R8A7795_CLK_MSO),
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 	DEF_MOD("msiof1",		 210,	R8A7795_CLK_MSO),
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 	DEF_MOD("msiof0",		 211,	R8A7795_CLK_MSO),
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-	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S0D3),
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-	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S0D3),
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+	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S3D1),
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+	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S3D1),
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 	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S0D3),
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 	DEF_MOD("sceg-pub",		 229,	R8A7795_CLK_CR),
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 	DEF_MOD("cmt3",			 300,	R8A7795_CLK_R),
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 	DEF_MOD("cmt2",			 301,	R8A7795_CLK_R),
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 	DEF_MOD("cmt1",			 302,	R8A7795_CLK_R),
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 	DEF_MOD("cmt0",			 303,	R8A7795_CLK_R),
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+	DEF_MOD("tpu0",			 304,	R8A7795_CLK_S3D4),
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 	DEF_MOD("scif2",		 310,	R8A7795_CLK_S3D4),
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 	DEF_MOD("sdif3",		 311,	R8A7795_CLK_SD3),
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 	DEF_MOD("sdif2",		 312,	R8A7795_CLK_SD2),
..
..
@@ -154,16 +162,16 @@
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 	DEF_MOD("rwdt",			 402,	R8A7795_CLK_R),
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 	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),
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 	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S0D3),
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-	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S0D3),
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-	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S0D3),
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-	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),
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-	DEF_MOD("drif6",		 509,	R8A7795_CLK_S3D2),
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-	DEF_MOD("drif5",		 510,	R8A7795_CLK_S3D2),
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-	DEF_MOD("drif4",		 511,	R8A7795_CLK_S3D2),
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-	DEF_MOD("drif3",		 512,	R8A7795_CLK_S3D2),
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-	DEF_MOD("drif2",		 513,	R8A7795_CLK_S3D2),
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-	DEF_MOD("drif1",		 514,	R8A7795_CLK_S3D2),
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-	DEF_MOD("drif0",		 515,	R8A7795_CLK_S3D2),
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+	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S1D2),
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+	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S1D2),
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+	DEF_MOD("drif31",		 508,	R8A7795_CLK_S3D2),
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+	DEF_MOD("drif30",		 509,	R8A7795_CLK_S3D2),
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+	DEF_MOD("drif21",		 510,	R8A7795_CLK_S3D2),
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+	DEF_MOD("drif20",		 511,	R8A7795_CLK_S3D2),
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+	DEF_MOD("drif11",		 512,	R8A7795_CLK_S3D2),
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+	DEF_MOD("drif10",		 513,	R8A7795_CLK_S3D2),
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+	DEF_MOD("drif01",		 514,	R8A7795_CLK_S3D2),
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+	DEF_MOD("drif00",		 515,	R8A7795_CLK_S3D2),
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 	DEF_MOD("hscif4",		 516,	R8A7795_CLK_S3D1),
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 	DEF_MOD("hscif3",		 517,	R8A7795_CLK_S3D1),
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 	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),
..
..
@@ -195,12 +203,16 @@
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 	DEF_MOD("vspi2",		 629,	R8A7795_CLK_S2D1), /* ES1.x */
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 	DEF_MOD("vspi1",		 630,	R8A7795_CLK_S0D1),
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 	DEF_MOD("vspi0",		 631,	R8A7795_CLK_S0D1),
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-	DEF_MOD("ehci3",		 700,	R8A7795_CLK_S3D4),
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-	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D4),
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-	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D4),
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-	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D4),
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-	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D4),
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-	DEF_MOD("hsusb3",		 705,	R8A7795_CLK_S3D4),
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+	DEF_MOD("ehci3",		 700,	R8A7795_CLK_S3D2),
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+	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D2),
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+	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D2),
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+	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D2),
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+	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D2),
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+	DEF_MOD("hsusb3",		 705,	R8A7795_CLK_S3D2),
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+	DEF_MOD("cmm3",			 708,	R8A7795_CLK_S2D1),
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+	DEF_MOD("cmm2",			 709,	R8A7795_CLK_S2D1),
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+	DEF_MOD("cmm1",			 710,	R8A7795_CLK_S2D1),
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+	DEF_MOD("cmm0",			 711,	R8A7795_CLK_S2D1),
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 	DEF_MOD("csi21",		 713,	R8A7795_CLK_CSI0), /* ES1.x */
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 	DEF_MOD("csi20",		 714,	R8A7795_CLK_CSI0),
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 	DEF_MOD("csi41",		 715,	R8A7795_CLK_CSI0),
..
..
@@ -237,6 +249,7 @@
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 	DEF_MOD("can-fd",		 914,	R8A7795_CLK_S3D2),
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 	DEF_MOD("can-if1",		 915,	R8A7795_CLK_S3D4),
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 	DEF_MOD("can-if0",		 916,	R8A7795_CLK_S3D4),
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+	DEF_MOD("rpc-if",		 917,	R8A7795_CLK_RPCD2),
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 	DEF_MOD("i2c6",			 918,	R8A7795_CLK_S0D6),
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 	DEF_MOD("i2c5",			 919,	R8A7795_CLK_S0D6),
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 	DEF_MOD("i2c-dvfs",		 926,	R8A7795_CLK_CP),
..
..
@@ -274,34 +287,34 @@
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 };
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 static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
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+	MOD_CLK_ID(402),	/* RWDT */
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 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
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 };
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-
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 /*
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  * CPG Clock Data
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  */
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 /*
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- *   MD		EXTAL		PLL0	PLL1	PLL2	PLL3	PLL4
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+ *   MD		EXTAL		PLL0	PLL1	PLL2	PLL3	PLL4	OSC
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  * 14 13 19 17	(MHz)
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- *-------------------------------------------------------------------
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- * 0  0  0  0	16.66 x 1	x180	x192	x144	x192	x144
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- * 0  0  0  1	16.66 x 1	x180	x192	x144	x128	x144
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+ *-------------------------------------------------------------------------
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+ * 0  0  0  0	16.66 x 1	x180	x192	x144	x192	x144	/16
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+ * 0  0  0  1	16.66 x 1	x180	x192	x144	x128	x144	/16
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  * 0  0  1  0	Prohibited setting
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- * 0  0  1  1	16.66 x 1	x180	x192	x144	x192	x144
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- * 0  1  0  0	20    x 1	x150	x160	x120	x160	x120
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- * 0  1  0  1	20    x 1	x150	x160	x120	x106	x120
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+ * 0  0  1  1	16.66 x 1	x180	x192	x144	x192	x144	/16
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+ * 0  1  0  0	20    x 1	x150	x160	x120	x160	x120	/19
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+ * 0  1  0  1	20    x 1	x150	x160	x120	x106	x120	/19
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  * 0  1  1  0	Prohibited setting
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- * 0  1  1  1	20    x 1	x150	x160	x120	x160	x120
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- * 1  0  0  0	25    x 1	x120	x128	x96	x128	x96
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- * 1  0  0  1	25    x 1	x120	x128	x96	x84	x96
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+ * 0  1  1  1	20    x 1	x150	x160	x120	x160	x120	/19
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+ * 1  0  0  0	25    x 1	x120	x128	x96	x128	x96	/24
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+ * 1  0  0  1	25    x 1	x120	x128	x96	x84	x96	/24
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  * 1  0  1  0	Prohibited setting
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- * 1  0  1  1	25    x 1	x120	x128	x96	x128	x96
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- * 1  1  0  0	33.33 / 2	x180	x192	x144	x192	x144
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- * 1  1  0  1	33.33 / 2	x180	x192	x144	x128	x144
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+ * 1  0  1  1	25    x 1	x120	x128	x96	x128	x96	/24
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+ * 1  1  0  0	33.33 / 2	x180	x192	x144	x192	x144	/32
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+ * 1  1  0  1	33.33 / 2	x180	x192	x144	x128	x144	/32
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  * 1  1  1  0	Prohibited setting
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- * 1  1  1  1	33.33 / 2	x180	x192	x144	x192	x144
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+ * 1  1  1  1	33.33 / 2	x180	x192	x144	x192	x144	/32
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  */
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 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 11) | \
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 					 (((md) & BIT(13)) >> 11) | \
..
..
@@ -309,23 +322,23 @@
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 					 (((md) & BIT(17)) >> 17))
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323
 
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 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
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-	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
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-	{ 1,		192,	1,	192,	1,	},
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-	{ 1,		192,	1,	128,	1,	},
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-	{ 0, /* Prohibited setting */			},
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-	{ 1,		192,	1,	192,	1,	},
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-	{ 1,		160,	1,	160,	1,	},
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-	{ 1,		160,	1,	106,	1,	},
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-	{ 0, /* Prohibited setting */			},
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-	{ 1,		160,	1,	160,	1,	},
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-	{ 1,		128,	1,	128,	1,	},
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-	{ 1,		128,	1,	84,	1,	},
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-	{ 0, /* Prohibited setting */			},
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-	{ 1,		128,	1,	128,	1,	},
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-	{ 2,		192,	1,	192,	1,	},
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-	{ 2,		192,	1,	128,	1,	},
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-	{ 0, /* Prohibited setting */			},
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-	{ 2,		192,	1,	192,	1,	},
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+	/* EXTAL div	PLL1 mult/div	PLL3 mult/div	OSC prediv */
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+	{ 1,		192,	1,	192,	1,	16,	},
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+	{ 1,		192,	1,	128,	1,	16,	},
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+	{ 0, /* Prohibited setting */				},
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+	{ 1,		192,	1,	192,	1,	16,	},
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+	{ 1,		160,	1,	160,	1,	19,	},
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+	{ 1,		160,	1,	106,	1,	19,	},
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+	{ 0, /* Prohibited setting */				},
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+	{ 1,		160,	1,	160,	1,	19,	},
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+	{ 1,		128,	1,	128,	1,	24,	},
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+	{ 1,		128,	1,	84,	1,	24,	},
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+	{ 0, /* Prohibited setting */				},
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+	{ 1,		128,	1,	128,	1,	24,	},
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+	{ 2,		192,	1,	192,	1,	32,	},
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+	{ 2,		192,	1,	128,	1,	32,	},
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+	{ 0, /* Prohibited setting */				},
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+	{ 2,		192,	1,	192,	1,	32,	},
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 };
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 static const struct soc_device_attribute r8a7795es1[] __initconst = {