write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/clk/qcom/gpucc-sc7180.c
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@@ -21,8 +21,6 @@
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 #define CX_GMU_CBCR_SLEEP_SHIFT		4
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 #define CX_GMU_CBCR_WAKE_MASK		0xF
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 #define CX_GMU_CBCR_WAKE_SHIFT		8
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-#define CLK_DIS_WAIT_SHIFT		12
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-#define CLK_DIS_WAIT_MASK		(0xf << CLK_DIS_WAIT_SHIFT)
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 enum {
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 	P_BI_TCXO,
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@@ -163,6 +161,7 @@
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 static struct gdsc cx_gdsc = {
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 	.gdscr = 0x106c,
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 	.gds_hw_ctrl = 0x1540,
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+	.clk_dis_wait_val = 8,
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 	.pd = {
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 		.name = "cx_gdsc",
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 	},
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@@ -244,10 +243,6 @@
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 	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
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 	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
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 	regmap_update_bits(regmap, 0x1098, mask, value);
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-
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-	/* Configure clk_dis_wait for gpu_cx_gdsc */
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-	regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
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-						8 << CLK_DIS_WAIT_SHIFT);
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 	return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
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 }