write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/clk/qcom/gdsc.h
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@@ -1,14 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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- * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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+ * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
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  */
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 #ifndef __QCOM_GDSC_H__
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@@ -18,6 +10,7 @@
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 #include <linux/pm_domain.h>
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 struct regmap;
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+struct regulator;
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 struct reset_controller_dev;
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 /**
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@@ -29,6 +22,9 @@
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  * @cxcs: offsets of branch registers to toggle mem/periph bits in
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  * @cxc_count: number of @cxcs
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  * @pwrsts: Possible powerdomain power states
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+ * @en_rest_wait_val: transition delay value for receiving enr ack signal
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+ * @en_few_wait_val: transition delay value for receiving enf ack signal
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+ * @clk_dis_wait_val: transition delay value for halting clock
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  * @resets: ids of resets associated with this gdsc
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  * @reset_count: number of @resets
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  * @rcdev: reset controller
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@@ -42,6 +38,9 @@
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 	unsigned int			clamp_io_ctrl;
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 	unsigned int			*cxcs;
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 	unsigned int			cxc_count;
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+	unsigned int			en_rest_wait_val;
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+	unsigned int			en_few_wait_val;
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+	unsigned int			clk_dis_wait_val;
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 	const u8			pwrsts;
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 /* Powerdomain allowable state bitfields */
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 #define PWRSTS_OFF		BIT(0)
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@@ -49,7 +48,7 @@
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 #define PWRSTS_ON		BIT(2)
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 #define PWRSTS_OFF_ON		(PWRSTS_OFF | PWRSTS_ON)
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 #define PWRSTS_RET_ON		(PWRSTS_RET | PWRSTS_ON)
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-	const u8			flags;
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+	const u16			flags;
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 #define VOTABLE		BIT(0)
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 #define CLAMP_IO	BIT(1)
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 #define HW_CTRL		BIT(2)
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@@ -57,9 +56,14 @@
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 #define AON_RESET	BIT(4)
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 #define POLL_CFG_GDSCR	BIT(5)
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 #define ALWAYS_ON	BIT(6)
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+#define RETAIN_FF_ENABLE	BIT(7)
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+#define NO_RET_PERIPH	BIT(8)
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 	struct reset_controller_dev	*rcdev;
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 	unsigned int			*resets;
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 	unsigned int			reset_count;
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+
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+	const char 			*supply;
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+	struct regulator		*rsupply;
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 };
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 struct gdsc_desc {
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@@ -72,6 +76,7 @@
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 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
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 		  struct regmap *);
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 void gdsc_unregister(struct gdsc_desc *desc);
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+int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
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 #else
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 static inline int gdsc_register(struct gdsc_desc *desc,
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 				struct reset_controller_dev *rcdev,