write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/clk/meson/axg-aoclk.c
..
..
@@ -12,9 +12,25 @@
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 #include <linux/platform_device.h>
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 #include <linux/reset-controller.h>
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 #include <linux/mfd/syscon.h>
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-#include "clk-regmap.h"
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+#include <linux/module.h>
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 #include "meson-aoclk.h"
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 #include "axg-aoclk.h"
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+
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+#include "clk-regmap.h"
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+#include "clk-dualdiv.h"
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+
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+/*
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+ * AO Configuration Clock registers offsets
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+ * Register offsets from the data sheet must be multiplied by 4.
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+ */
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+#define AO_RTI_PWR_CNTL_REG1	0x0C
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+#define AO_RTI_PWR_CNTL_REG0	0x10
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+#define AO_RTI_GEN_CNTL_REG0	0x40
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+#define AO_OSCIN_CNTL		0x58
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+#define AO_CRT_CLK_CNTL1	0x68
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+#define AO_SAR_CLK		0x90
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+#define AO_RTC_ALT_CLK_CNTL0	0x94
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+#define AO_RTC_ALT_CLK_CNTL1	0x98
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 #define AXG_AO_GATE(_name, _bit)					\
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 static struct clk_regmap axg_aoclk_##_name = {				\
..
..
@@ -25,7 +41,9 @@
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 	.hw.init = &(struct clk_init_data) {				\
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 		.name =  "axg_ao_" #_name,				\
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 		.ops = &clk_regmap_gate_ops,				\
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-		.parent_names = (const char *[]){ "clk81" },		\
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+		.parent_data = &(const struct clk_parent_data) {	\
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+			.fw_name = "mpeg-clk",				\
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+		},							\
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 		.num_parents = 1,					\
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 		.flags = CLK_IGNORE_UNUSED,				\
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 	},								\
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..
@@ -39,17 +57,155 @@
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 AXG_AO_GATE(ir_blaster, 6);
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 AXG_AO_GATE(saradc, 7);
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+static struct clk_regmap axg_aoclk_cts_oscin = {
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+	.data = &(struct clk_regmap_gate_data){
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+		.offset = AO_RTI_PWR_CNTL_REG0,
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+		.bit_idx = 14,
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+	},
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+	.hw.init = &(struct clk_init_data){
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+		.name = "cts_oscin",
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+		.ops = &clk_regmap_gate_ro_ops,
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+		.parent_data = &(const struct clk_parent_data) {
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+			.fw_name = "xtal",
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+		},
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+		.num_parents = 1,
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+	},
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+};
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+
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+static struct clk_regmap axg_aoclk_32k_pre = {
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+	.data = &(struct clk_regmap_gate_data){
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+		.offset = AO_RTC_ALT_CLK_CNTL0,
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+		.bit_idx = 31,
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+	},
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+	.hw.init = &(struct clk_init_data){
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+		.name = "axg_ao_32k_pre",
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+		.ops = &clk_regmap_gate_ops,
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+		.parent_hws = (const struct clk_hw *[]) {
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+			&axg_aoclk_cts_oscin.hw
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+		},
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+		.num_parents = 1,
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+	},
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+};
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+
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+static const struct meson_clk_dualdiv_param axg_32k_div_table[] = {
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+	{
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+		.dual	= 1,
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+		.n1	= 733,
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+		.m1	= 8,
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+		.n2	= 732,
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+		.m2	= 11,
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+	}, {}
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+};
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+
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+static struct clk_regmap axg_aoclk_32k_div = {
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+	.data = &(struct meson_clk_dualdiv_data){
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+		.n1 = {
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+			.reg_off = AO_RTC_ALT_CLK_CNTL0,
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+			.shift   = 0,
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+			.width   = 12,
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+		},
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+		.n2 = {
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+			.reg_off = AO_RTC_ALT_CLK_CNTL0,
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+			.shift   = 12,
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+			.width   = 12,
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+		},
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+		.m1 = {
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+			.reg_off = AO_RTC_ALT_CLK_CNTL1,
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+			.shift   = 0,
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+			.width   = 12,
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+		},
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+		.m2 = {
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+			.reg_off = AO_RTC_ALT_CLK_CNTL1,
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+			.shift   = 12,
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+			.width   = 12,
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+		},
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+		.dual = {
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+			.reg_off = AO_RTC_ALT_CLK_CNTL0,
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+			.shift   = 28,
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+			.width   = 1,
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+		},
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+		.table = axg_32k_div_table,
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+	},
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+	.hw.init = &(struct clk_init_data){
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+		.name = "axg_ao_32k_div",
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+		.ops = &meson_clk_dualdiv_ops,
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+		.parent_hws = (const struct clk_hw *[]) {
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+			&axg_aoclk_32k_pre.hw
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+		},
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+		.num_parents = 1,
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+	},
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+};
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+
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+static struct clk_regmap axg_aoclk_32k_sel = {
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+	.data = &(struct clk_regmap_mux_data) {
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+		.offset = AO_RTC_ALT_CLK_CNTL1,
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+		.mask = 0x1,
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+		.shift = 24,
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+		.flags = CLK_MUX_ROUND_CLOSEST,
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+	},
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+	.hw.init = &(struct clk_init_data){
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+		.name = "axg_ao_32k_sel",
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+		.ops = &clk_regmap_mux_ops,
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+		.parent_hws = (const struct clk_hw *[]) {
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+			&axg_aoclk_32k_div.hw,
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+			&axg_aoclk_32k_pre.hw,
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+		},
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+		.num_parents = 2,
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+		.flags = CLK_SET_RATE_PARENT,
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+	},
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+};
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+
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+static struct clk_regmap axg_aoclk_32k = {
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+	.data = &(struct clk_regmap_gate_data){
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+		.offset = AO_RTC_ALT_CLK_CNTL0,
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+		.bit_idx = 30,
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+	},
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+	.hw.init = &(struct clk_init_data){
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+		.name = "axg_ao_32k",
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+		.ops = &clk_regmap_gate_ops,
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+		.parent_hws = (const struct clk_hw *[]) {
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+			&axg_aoclk_32k_sel.hw
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+		},
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+		.num_parents = 1,
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+		.flags = CLK_SET_RATE_PARENT,
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+	},
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+};
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+
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+static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
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+	.data = &(struct clk_regmap_mux_data) {
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+		.offset = AO_RTI_PWR_CNTL_REG0,
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+		.mask = 0x1,
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+		.shift = 10,
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+		.flags = CLK_MUX_ROUND_CLOSEST,
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+	},
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+	.hw.init = &(struct clk_init_data){
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+		.name = "axg_ao_cts_rtc_oscin",
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+		.ops = &clk_regmap_mux_ops,
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+		.parent_data = (const struct clk_parent_data []) {
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+			{ .hw = &axg_aoclk_32k.hw },
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+			{ .fw_name = "ext_32k-0", },
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+		},
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+		.num_parents = 2,
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+		.flags = CLK_SET_RATE_PARENT,
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+	},
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+};
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+
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 static struct clk_regmap axg_aoclk_clk81 = {
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 	.data = &(struct clk_regmap_mux_data) {
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 		.offset = AO_RTI_PWR_CNTL_REG0,
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 		.mask = 0x1,
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 		.shift = 8,
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+		.flags = CLK_MUX_ROUND_CLOSEST,
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 	},
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 	.hw.init = &(struct clk_init_data){
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 		.name = "axg_ao_clk81",
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 		.ops = &clk_regmap_mux_ro_ops,
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-		.parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
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+		.parent_data = (const struct clk_parent_data []) {
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+			{ .fw_name = "mpeg-clk", },
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+			{ .hw = &axg_aoclk_cts_rtc_oscin.hw },
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+		},
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 		.num_parents = 2,
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+		.flags = CLK_SET_RATE_PARENT,
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 	},
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 };
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..
..
@@ -62,7 +218,10 @@
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 	.hw.init = &(struct clk_init_data){
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 		.name = "axg_ao_saradc_mux",
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 		.ops = &clk_regmap_mux_ops,
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-		.parent_names = (const char *[]){ "xtal", "axg_ao_clk81" },
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+		.parent_data = (const struct clk_parent_data []) {
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+			{ .fw_name = "xtal", },
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+			{ .hw = &axg_aoclk_clk81.hw },
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+		},
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 		.num_parents = 2,
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 	},
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 };
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@@ -76,7 +235,9 @@
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 	.hw.init = &(struct clk_init_data){
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 		.name = "axg_ao_saradc_div",
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 		.ops = &clk_regmap_divider_ops,
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-		.parent_names = (const char *[]){ "axg_ao_saradc_mux" },
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+		.parent_hws = (const struct clk_hw *[]) {
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+			&axg_aoclk_saradc_mux.hw
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+		},
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 		.num_parents = 1,
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 		.flags = CLK_SET_RATE_PARENT,
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 	},
..
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@@ -90,7 +251,9 @@
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 	.hw.init = &(struct clk_init_data){
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 		.name = "axg_ao_saradc_gate",
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 		.ops = &clk_regmap_gate_ops,
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-		.parent_names = (const char *[]){ "axg_ao_saradc_div" },
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+		.parent_hws = (const struct clk_hw *[]) {
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+			&axg_aoclk_saradc_div.hw
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+		},
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 		.num_parents = 1,
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 		.flags = CLK_SET_RATE_PARENT,
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 	},
..
..
@@ -106,17 +269,23 @@
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 };
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 static struct clk_regmap *axg_aoclk_regmap[] = {
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-	[CLKID_AO_REMOTE]	= &axg_aoclk_remote,
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-	[CLKID_AO_I2C_MASTER]	= &axg_aoclk_i2c_master,
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-	[CLKID_AO_I2C_SLAVE]	= &axg_aoclk_i2c_slave,
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-	[CLKID_AO_UART1]	= &axg_aoclk_uart1,
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-	[CLKID_AO_UART2]	= &axg_aoclk_uart2,
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-	[CLKID_AO_IR_BLASTER]	= &axg_aoclk_ir_blaster,
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-	[CLKID_AO_SAR_ADC]	= &axg_aoclk_saradc,
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-	[CLKID_AO_CLK81]	= &axg_aoclk_clk81,
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-	[CLKID_AO_SAR_ADC_SEL]	= &axg_aoclk_saradc_mux,
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-	[CLKID_AO_SAR_ADC_DIV]	= &axg_aoclk_saradc_div,
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-	[CLKID_AO_SAR_ADC_CLK]	= &axg_aoclk_saradc_gate,
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+	&axg_aoclk_remote,
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+	&axg_aoclk_i2c_master,
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+	&axg_aoclk_i2c_slave,
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+	&axg_aoclk_uart1,
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+	&axg_aoclk_uart2,
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+	&axg_aoclk_ir_blaster,
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+	&axg_aoclk_saradc,
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+	&axg_aoclk_cts_oscin,
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+	&axg_aoclk_32k_pre,
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+	&axg_aoclk_32k_div,
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+	&axg_aoclk_32k_sel,
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+	&axg_aoclk_32k,
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+	&axg_aoclk_cts_rtc_oscin,
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+	&axg_aoclk_clk81,
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+	&axg_aoclk_saradc_mux,
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+	&axg_aoclk_saradc_div,
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+	&axg_aoclk_saradc_gate,
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 };
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 static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
..
..
@@ -132,6 +301,12 @@
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 		[CLKID_AO_SAR_ADC_SEL]	= &axg_aoclk_saradc_mux.hw,
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 		[CLKID_AO_SAR_ADC_DIV]	= &axg_aoclk_saradc_div.hw,
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 		[CLKID_AO_SAR_ADC_CLK]	= &axg_aoclk_saradc_gate.hw,
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+		[CLKID_AO_CTS_OSCIN]	= &axg_aoclk_cts_oscin.hw,
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+		[CLKID_AO_32K_PRE]	= &axg_aoclk_32k_pre.hw,
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+		[CLKID_AO_32K_DIV]	= &axg_aoclk_32k_div.hw,
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+		[CLKID_AO_32K_SEL]	= &axg_aoclk_32k_sel.hw,
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+		[CLKID_AO_32K]		= &axg_aoclk_32k.hw,
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+		[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
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 	},
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 	.num = NR_CLKS,
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 };
..
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@@ -152,6 +327,7 @@
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 	},
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 	{ }
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 };
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+MODULE_DEVICE_TABLE(of, axg_aoclkc_match_table);
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 static struct platform_driver axg_aoclkc_driver = {
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 	.probe		= meson_aoclkc_probe,
..
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@@ -161,4 +337,5 @@
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 	},
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 };
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-builtin_platform_driver(axg_aoclkc_driver);
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+module_platform_driver(axg_aoclkc_driver);
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+MODULE_LICENSE("GPL v2");