write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/clk/clk-hsdk-pll.c
..
..
@@ -12,6 +12,7 @@
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 #include <linux/delay.h>
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 #include <linux/device.h>
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 #include <linux/err.h>
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+#include <linux/io.h>
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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 #include <linux/of_device.h>
..
..
@@ -52,35 +53,38 @@
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 	u32 fbdiv;
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 	u32 odiv;
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 	u32 band;
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+	u32 bypass;
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 };
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58
 
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 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
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-	{ 100000000,  0, 11, 3, 0 },
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-	{ 133000000,  0, 15, 3, 0 },
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-	{ 200000000,  1, 47, 3, 0 },
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-	{ 233000000,  1, 27, 2, 0 },
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-	{ 300000000,  1, 35, 2, 0 },
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-	{ 333000000,  1, 39, 2, 0 },
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-	{ 400000000,  1, 47, 2, 0 },
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-	{ 500000000,  0, 14, 1, 0 },
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-	{ 600000000,  0, 17, 1, 0 },
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-	{ 700000000,  0, 20, 1, 0 },
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-	{ 800000000,  0, 23, 1, 0 },
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-	{ 900000000,  1, 26, 0, 0 },
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-	{ 1000000000, 1, 29, 0, 0 },
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-	{ 1100000000, 1, 32, 0, 0 },
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-	{ 1200000000, 1, 35, 0, 0 },
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-	{ 1300000000, 1, 38, 0, 0 },
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-	{ 1400000000, 1, 41, 0, 0 },
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-	{ 1500000000, 1, 44, 0, 0 },
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-	{ 1600000000, 1, 47, 0, 0 },
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+	{ 100000000,  0, 11, 3, 0, 0 },
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+	{ 133000000,  0, 15, 3, 0, 0 },
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+	{ 200000000,  1, 47, 3, 0, 0 },
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+	{ 233000000,  1, 27, 2, 0, 0 },
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+	{ 300000000,  1, 35, 2, 0, 0 },
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+	{ 333000000,  1, 39, 2, 0, 0 },
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+	{ 400000000,  1, 47, 2, 0, 0 },
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+	{ 500000000,  0, 14, 1, 0, 0 },
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+	{ 600000000,  0, 17, 1, 0, 0 },
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+	{ 700000000,  0, 20, 1, 0, 0 },
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+	{ 800000000,  0, 23, 1, 0, 0 },
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+	{ 900000000,  1, 26, 0, 0, 0 },
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+	{ 1000000000, 1, 29, 0, 0, 0 },
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+	{ 1100000000, 1, 32, 0, 0, 0 },
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+	{ 1200000000, 1, 35, 0, 0, 0 },
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+	{ 1300000000, 1, 38, 0, 0, 0 },
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+	{ 1400000000, 1, 41, 0, 0, 0 },
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+	{ 1500000000, 1, 44, 0, 0, 0 },
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+	{ 1600000000, 1, 47, 0, 0, 0 },
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 	{}
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 };
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81
 
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 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
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-	{ 297000000,  0, 21, 2, 0 },
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-	{ 540000000,  0, 19, 1, 0 },
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-	{ 594000000,  0, 21, 1, 0 },
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+	{ 27000000,   0, 0,  0, 0, 1 },
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+	{ 148500000,  0, 21, 3, 0, 0 },
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+	{ 297000000,  0, 21, 2, 0, 0 },
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+	{ 540000000,  0, 19, 1, 0, 0 },
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+	{ 594000000,  0, 21, 1, 0, 0 },
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 	{}
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 };
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..
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@@ -133,11 +137,16 @@
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 {
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 	u32 val = 0;
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-	/* Powerdown and Bypass bits should be cleared */
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-	val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
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-	val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
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-	val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
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-	val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
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+	if (cfg->bypass) {
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+		val = hsdk_pll_read(clk, CGU_PLL_CTRL);
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+		val |= CGU_PLL_CTRL_BYPASS;
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+	} else {
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+		/* Powerdown and Bypass bits should be cleared */
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+		val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
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+		val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
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+		val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
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+		val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
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+	}
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 	dev_dbg(clk->dev, "write configuration: %#x\n", val);
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..
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@@ -171,13 +180,13 @@
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180
 
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 	dev_dbg(clk->dev, "current configuration: %#x\n", val);
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182
 
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-	/* Check if PLL is disabled */
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-	if (val & CGU_PLL_CTRL_PD)
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-		return 0;
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-
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 	/* Check if PLL is bypassed */
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 	if (val & CGU_PLL_CTRL_BYPASS)
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 		return parent_rate;
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+
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+	/* Check if PLL is disabled */
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+	if (val & CGU_PLL_CTRL_PD)
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+		return 0;
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 	/* input divider = reg.idiv + 1 */
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 	idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
..
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@@ -390,13 +399,13 @@
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 	ret = clk_hw_register(NULL, &pll_clk->hw);
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 	if (ret) {
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-		pr_err("failed to register %s clock\n", node->name);
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+		pr_err("failed to register %pOFn clock\n", node);
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 		goto err_unmap_spec_regs;
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 	}
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 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
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 	if (ret) {
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-		pr_err("failed to add hw provider for %s clock\n", node->name);
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+		pr_err("failed to add hw provider for %pOFn clock\n", node);
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 		goto err_unmap_spec_regs;
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 	}
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