write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/drivers/clk/clk-gate.c
..
..
@@ -1,10 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0
1
2
 /*
2
3
  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3
4
  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
5
  *
9
6
  * Gated clock implementation
10
7
  */
..
..
@@ -30,6 +27,22 @@
30
27
  * parent - fixed parent.  No clk_set_parent support
31
28
  */
32
29
 
30
+static inline u32 clk_gate_readl(struct clk_gate *gate)
31
+{
32
+	if (gate->flags & CLK_GATE_BIG_ENDIAN)
33
+		return ioread32be(gate->reg);
34
+
35
+	return readl(gate->reg);
36
+}
37
+
38
+static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
39
+{
40
+	if (gate->flags & CLK_GATE_BIG_ENDIAN)
41
+		iowrite32be(val, gate->reg);
42
+	else
43
+		writel(val, gate->reg);
44
+}
45
+
33
46
 /*
34
47
  * It works on following logic:
35
48
  *
..
..
@@ -47,7 +60,7 @@
47
60
 {
48
61
 	struct clk_gate *gate = to_clk_gate(hw);
49
62
 	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
50
-	unsigned long uninitialized_var(flags);
63
+	unsigned long flags;
51
64
 	u32 reg;
52
65
 
53
66
 	if (clk_always_on && !enable)
..
..
@@ -65,7 +78,7 @@
65
78
 		if (set)
66
79
 			reg |= BIT(gate->bit_idx);
67
80
 	} else {
68
-		reg = clk_readl(gate->reg);
81
+		reg = clk_gate_readl(gate);
69
82
 
70
83
 		if (set)
71
84
 			reg |= BIT(gate->bit_idx);
..
..
@@ -73,7 +86,7 @@
73
86
 			reg &= ~BIT(gate->bit_idx);
74
87
 	}
75
88
 
76
-	clk_writel(reg, gate->reg);
89
+	clk_gate_writel(gate, reg);
77
90
 
78
91
 	if (gate->lock)
79
92
 		spin_unlock_irqrestore(gate->lock, flags);
..
..
@@ -98,7 +111,7 @@
98
111
 	u32 reg;
99
112
 	struct clk_gate *gate = to_clk_gate(hw);
100
113
 
101
-	reg = clk_readl(gate->reg);
114
+	reg = clk_gate_readl(gate);
102
115
 
103
116
 	/* if a set bit disables this clk, flip it before masking */
104
117
 	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
..
..
@@ -117,26 +130,18 @@
117
130
 };
118
131
 EXPORT_SYMBOL_GPL(clk_gate_ops);
119
132
 
120
-/**
121
- * clk_hw_register_gate - register a gate clock with the clock framework
122
- * @dev: device that is registering this clock
123
- * @name: name of this clock
124
- * @parent_name: name of this clock's parent
125
- * @flags: framework-specific flags for this clock
126
- * @reg: register address to control gating of this clock
127
- * @bit_idx: which bit in the register controls gating of this clock
128
- * @clk_gate_flags: gate-specific flags for this clock
129
- * @lock: shared register lock for this clock
130
- */
131
-struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
132
-		const char *parent_name, unsigned long flags,
133
+struct clk_hw *__clk_hw_register_gate(struct device *dev,
134
+		struct device_node *np, const char *name,
135
+		const char *parent_name, const struct clk_hw *parent_hw,
136
+		const struct clk_parent_data *parent_data,
137
+		unsigned long flags,
133
138
 		void __iomem *reg, u8 bit_idx,
134
139
 		u8 clk_gate_flags, spinlock_t *lock)
135
140
 {
136
141
 	struct clk_gate *gate;
137
142
 	struct clk_hw *hw;
138
143
 	struct clk_init_data init = {};
139
-	int ret;
144
+	int ret = -EINVAL;
140
145
 
141
146
 	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
142
147
 		if (bit_idx > 15) {
..
..
@@ -152,9 +157,14 @@
152
157
 
153
158
 	init.name = name;
154
159
 	init.ops = &clk_gate_ops;
155
-	init.flags = flags | CLK_IS_BASIC;
160
+	init.flags = flags;
156
161
 	init.parent_names = parent_name ? &parent_name : NULL;
157
-	init.num_parents = parent_name ? 1 : 0;
162
+	init.parent_hws = parent_hw ? &parent_hw : NULL;
163
+	init.parent_data = parent_data;
164
+	if (parent_name || parent_hw || parent_data)
165
+		init.num_parents = 1;
166
+	else
167
+		init.num_parents = 0;
158
168
 
159
169
 	/* struct clk_gate assignments */
160
170
 	gate->reg = reg;
..
..
@@ -164,15 +174,19 @@
164
174
 	gate->hw.init = &init;
165
175
 
166
176
 	hw = &gate->hw;
167
-	ret = clk_hw_register(dev, hw);
177
+	if (dev || !np)
178
+		ret = clk_hw_register(dev, hw);
179
+	else if (np)
180
+		ret = of_clk_hw_register(np, hw);
168
181
 	if (ret) {
169
182
 		kfree(gate);
170
183
 		hw = ERR_PTR(ret);
171
184
 	}
172
185
 
173
186
 	return hw;
187
+
174
188
 }
175
-EXPORT_SYMBOL_GPL(clk_hw_register_gate);
189
+EXPORT_SYMBOL_GPL(__clk_hw_register_gate);
176
190
 
177
191
 struct clk *clk_register_gate(struct device *dev, const char *name,
178
192
 		const char *parent_name, unsigned long flags,