| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * drivers/clk/clk-axm5516.c |
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| 3 | 4 | * |
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| .. | .. |
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| 5 | 6 | * the Axxia device: PLL clock, a clock divider and a clock mux. |
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| 6 | 7 | * |
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| 7 | 8 | * Copyright (C) 2014 LSI Corporation |
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| 8 | | - * |
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| 9 | | - * This program is free software; you can redistribute it and/or modify it |
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| 10 | | - * under the terms of the GNU General Public License version 2 as published by |
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| 11 | | - * the Free Software Foundation. |
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| 12 | 9 | */ |
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| 13 | 10 | #include <linux/module.h> |
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| 14 | 11 | #include <linux/kernel.h> |
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| .. | .. |
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| 311 | 308 | "clk_sm1_pll" |
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| 312 | 309 | }, |
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| 313 | 310 | .num_parents = 1, |
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| 314 | | - .flags = CLK_IS_BASIC, |
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| 315 | 311 | .ops = &axxia_divclk_ops, |
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| 316 | 312 | }, |
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| 317 | 313 | .reg = 0x1000c, |
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| .. | .. |
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| 326 | 322 | "clk_sm1_pll" |
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| 327 | 323 | }, |
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| 328 | 324 | .num_parents = 1, |
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| 329 | | - .flags = CLK_IS_BASIC, |
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| 330 | 325 | .ops = &axxia_divclk_ops, |
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| 331 | 326 | }, |
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| 332 | 327 | .reg = 0x1000c, |
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