| .. | .. |
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| 1 | +# SPDX-License-Identifier: GPL-2.0 |
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| 2 | + |
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| 3 | +config HAVE_CLK |
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| 4 | + bool |
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| 5 | + help |
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| 6 | + The <linux/clk.h> calls support software clock gating and |
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| 7 | + thus are a key power management tool on many systems. |
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| 1 | 8 | |
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| 2 | 9 | config CLKDEV_LOOKUP |
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| 3 | 10 | bool |
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| .. | .. |
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| 6 | 13 | config HAVE_CLK_PREPARE |
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| 7 | 14 | bool |
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| 8 | 15 | |
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| 9 | | -config COMMON_CLK |
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| 16 | +config HAVE_LEGACY_CLK # TODO: Remove once all legacy users are migrated |
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| 10 | 17 | bool |
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| 18 | + select HAVE_CLK |
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| 19 | + help |
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| 20 | + Select this option when the clock API in <linux/clk.h> is implemented |
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| 21 | + by platform/architecture code. This method is deprecated. Modern |
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| 22 | + code should select COMMON_CLK instead and not define a custom |
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| 23 | + 'struct clk'. |
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| 24 | + |
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| 25 | +menuconfig COMMON_CLK |
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| 26 | + bool "Common Clock Framework" |
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| 27 | + depends on !HAVE_LEGACY_CLK |
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| 11 | 28 | select HAVE_CLK_PREPARE |
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| 12 | 29 | select CLKDEV_LOOKUP |
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| 13 | 30 | select SRCU |
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| 14 | 31 | select RATIONAL |
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| 15 | | - ---help--- |
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| 32 | + help |
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| 16 | 33 | The common clock framework is a single definition of struct |
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| 17 | 34 | clk, useful across many platforms, as well as an |
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| 18 | 35 | implementation of the clock API in include/linux/clk.h. |
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| 19 | 36 | Architectures utilizing the common struct clk should select |
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| 20 | 37 | this option. |
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| 21 | 38 | |
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| 22 | | -menu "Common Clock Framework" |
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| 23 | | - depends on COMMON_CLK |
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| 24 | | - |
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| 25 | | -config COMMON_CLK_DEBUGFS |
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| 26 | | - bool "Common Clock DebugFS interface" |
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| 27 | | - depends on COMMON_CLK && DEBUG_FS |
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| 28 | | - default y |
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| 29 | | - help |
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| 30 | | - Turns on the DebugFS interface for clock. |
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| 39 | +if COMMON_CLK |
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| 31 | 40 | |
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| 32 | 41 | config COMMON_CLK_PROCFS |
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| 33 | 42 | bool "Common Clock PROCFS interface" |
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| 34 | | - depends on COMMON_CLK && PROC_FS |
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| 43 | + depends on COMMON_CLK && PROC_FS && ARCH_ROCKCHIP |
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| 35 | 44 | default n |
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| 36 | 45 | help |
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| 37 | 46 | Turns on the PROCFS interface for clock. |
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| .. | .. |
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| 39 | 48 | config COMMON_CLK_WM831X |
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| 40 | 49 | tristate "Clock driver for WM831x/2x PMICs" |
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| 41 | 50 | depends on MFD_WM831X |
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| 42 | | - ---help--- |
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| 43 | | - Supports the clocking subsystem of the WM831x/2x series of |
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| 51 | + help |
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| 52 | + Supports the clocking subsystem of the WM831x/2x series of |
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| 44 | 53 | PMICs from Wolfson Microelectronics. |
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| 45 | 54 | |
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| 46 | 55 | source "drivers/clk/versatile/Kconfig" |
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| 47 | 56 | |
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| 48 | 57 | config CLK_HSDK |
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| 49 | 58 | bool "PLL Driver for HSDK platform" |
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| 50 | | - depends on OF || COMPILE_TEST |
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| 51 | | - ---help--- |
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| 59 | + depends on ARC_SOC_HSDK || COMPILE_TEST |
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| 60 | + depends on HAS_IOMEM |
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| 61 | + help |
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| 52 | 62 | This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs |
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| 53 | 63 | control. |
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| 54 | 64 | |
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| 55 | 65 | config COMMON_CLK_MAX77686 |
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| 56 | 66 | tristate "Clock driver for Maxim 77620/77686/77802 MFD" |
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| 57 | 67 | depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST |
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| 58 | | - ---help--- |
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| 68 | + help |
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| 59 | 69 | This driver supports Maxim 77620/77686/77802 crystal oscillator |
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| 60 | 70 | clock. |
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| 61 | 71 | |
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| .. | .. |
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| 68 | 78 | config COMMON_CLK_RK808 |
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| 69 | 79 | tristate "Clock driver for RK805/RK808/RK809/RK817/RK818" |
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| 70 | 80 | depends on MFD_RK808 |
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| 71 | | - ---help--- |
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| 81 | + help |
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| 72 | 82 | This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock. |
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| 73 | 83 | These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. |
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| 74 | 84 | Clkout1 is always on, Clkout2 can off by control register. |
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| .. | .. |
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| 76 | 86 | config COMMON_CLK_HI655X |
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| 77 | 87 | tristate "Clock driver for Hi655x" if EXPERT |
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| 78 | 88 | depends on (MFD_HI655X_PMIC || COMPILE_TEST) |
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| 79 | | - depends on REGMAP |
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| 89 | + select REGMAP |
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| 80 | 90 | default MFD_HI655X_PMIC |
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| 81 | | - ---help--- |
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| 91 | + help |
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| 82 | 92 | This driver supports the hi655x PMIC clock. This |
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| 83 | 93 | multi-function device has one fixed-rate oscillator, clocked |
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| 84 | 94 | at 32KHz. |
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| .. | .. |
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| 86 | 96 | config COMMON_CLK_SCMI |
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| 87 | 97 | tristate "Clock driver controlled via SCMI interface" |
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| 88 | 98 | depends on ARM_SCMI_PROTOCOL || COMPILE_TEST |
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| 89 | | - ---help--- |
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| 99 | + help |
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| 90 | 100 | This driver provides support for clocks that are controlled |
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| 91 | 101 | by firmware that implements the SCMI interface. |
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| 92 | 102 | |
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| .. | .. |
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| 96 | 106 | config COMMON_CLK_SCPI |
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| 97 | 107 | tristate "Clock driver controlled via SCPI interface" |
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| 98 | 108 | depends on ARM_SCPI_PROTOCOL || COMPILE_TEST |
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| 99 | | - ---help--- |
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| 109 | + help |
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| 100 | 110 | This driver provides support for clocks that are controlled |
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| 101 | 111 | by firmware that implements the SCPI interface. |
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| 102 | 112 | |
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| 103 | 113 | This driver uses SCPI Message Protocol to interact with the |
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| 104 | 114 | firmware providing all the clock controls. |
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| 105 | 115 | |
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| 116 | +config COMMON_CLK_SI5341 |
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| 117 | + tristate "Clock driver for SiLabs 5341 and 5340 A/B/C/D devices" |
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| 118 | + depends on I2C |
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| 119 | + select REGMAP_I2C |
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| 120 | + help |
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| 121 | + This driver supports Silicon Labs Si5341 and Si5340 programmable clock |
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| 122 | + generators. Not all features of these chips are currently supported |
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| 123 | + by the driver, in particular it only supports XTAL input. The chip can |
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| 124 | + be pre-programmed to support other configurations and features not yet |
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| 125 | + implemented in the driver. |
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| 126 | + |
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| 106 | 127 | config COMMON_CLK_SI5351 |
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| 107 | 128 | tristate "Clock driver for SiLabs 5351A/B/C" |
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| 108 | 129 | depends on I2C |
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| 109 | 130 | select REGMAP_I2C |
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| 110 | | - select RATIONAL |
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| 111 | | - ---help--- |
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| 131 | + help |
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| 112 | 132 | This driver supports Silicon Labs 5351A/B/C programmable clock |
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| 113 | 133 | generators. |
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| 114 | 134 | |
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| .. | .. |
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| 118 | 138 | depends on OF |
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| 119 | 139 | select REGMAP_I2C |
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| 120 | 140 | help |
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| 121 | | - ---help--- |
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| 122 | 141 | This driver supports the Silicon Labs 514 programmable clock |
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| 123 | 142 | generator. |
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| 124 | 143 | |
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| .. | .. |
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| 127 | 146 | depends on I2C |
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| 128 | 147 | select REGMAP_I2C |
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| 129 | 148 | help |
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| 130 | | - ---help--- |
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| 131 | 149 | This driver supports the Silicon Labs 544 programmable clock |
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| 132 | 150 | generator. |
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| 133 | 151 | |
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| .. | .. |
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| 137 | 155 | depends on OF |
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| 138 | 156 | select REGMAP_I2C |
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| 139 | 157 | help |
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| 140 | | - ---help--- |
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| 141 | 158 | This driver supports Silicon Labs 570/571/598/599 programmable |
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| 142 | 159 | clock generators. |
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| 160 | + |
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| 161 | +config COMMON_CLK_BM1880 |
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| 162 | + bool "Clock driver for Bitmain BM1880 SoC" |
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| 163 | + depends on ARCH_BITMAIN || COMPILE_TEST |
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| 164 | + default ARCH_BITMAIN |
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| 165 | + help |
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| 166 | + This driver supports the clocks on Bitmain BM1880 SoC. |
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| 143 | 167 | |
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| 144 | 168 | config COMMON_CLK_CDCE706 |
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| 145 | 169 | tristate "Clock driver for TI CDCE706 clock synthesizer" |
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| 146 | 170 | depends on I2C |
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| 147 | 171 | select REGMAP_I2C |
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| 148 | | - select RATIONAL |
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| 149 | | - ---help--- |
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| 172 | + help |
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| 150 | 173 | This driver supports TI CDCE706 programmable 3-PLL clock synthesizer. |
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| 151 | 174 | |
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| 152 | 175 | config COMMON_CLK_CDCE925 |
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| .. | .. |
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| 155 | 178 | depends on OF |
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| 156 | 179 | select REGMAP_I2C |
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| 157 | 180 | help |
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| 158 | | - ---help--- |
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| 159 | 181 | This driver supports the TI CDCE913/925/937/949 programmable clock |
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| 160 | 182 | synthesizer. Each chip has different number of PLLs and outputs. |
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| 161 | 183 | For example, the CDCE925 contains two PLLs with spread-spectrum |
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| .. | .. |
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| 173 | 195 | help |
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| 174 | 196 | If you say yes here you get support for the CS2000 clock multiplier. |
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| 175 | 197 | |
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| 198 | +config COMMON_CLK_FSL_SAI |
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| 199 | + bool "Clock driver for BCLK of Freescale SAI cores" |
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| 200 | + depends on ARCH_LAYERSCAPE || COMPILE_TEST |
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| 201 | + help |
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| 202 | + This driver supports the Freescale SAI (Synchronous Audio Interface) |
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| 203 | + to be used as a generic clock output. Some SoCs have restrictions |
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| 204 | + regarding the possible pin multiplexer settings. Eg. on some SoCs |
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| 205 | + two SAI interfaces can only be enabled together. If just one is |
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| 206 | + needed, the BCLK pin of the second one can be used as general |
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| 207 | + purpose clock output. Ideally, it can be used to drive an audio |
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| 208 | + codec (sometimes known as MCLK). |
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| 209 | + |
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| 176 | 210 | config COMMON_CLK_GEMINI |
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| 177 | 211 | bool "Clock driver for Cortina Systems Gemini SoC" |
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| 178 | 212 | depends on ARCH_GEMINI || COMPILE_TEST |
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| 179 | 213 | select MFD_SYSCON |
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| 180 | 214 | select RESET_CONTROLLER |
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| 181 | | - ---help--- |
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| 215 | + help |
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| 182 | 216 | This driver supports the SoC clocks on the Cortina Systems Gemini |
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| 183 | 217 | platform, also known as SL3516 or CS3516. |
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| 184 | 218 | |
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| .. | .. |
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| 188 | 222 | default ARCH_ASPEED |
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| 189 | 223 | select MFD_SYSCON |
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| 190 | 224 | select RESET_CONTROLLER |
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| 191 | | - ---help--- |
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| 225 | + help |
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| 192 | 226 | This driver supports the SoC clocks on the Aspeed BMC platforms. |
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| 193 | 227 | |
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| 194 | 228 | The G4 and G5 series, including the ast2400 and ast2500, are supported |
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| .. | .. |
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| 197 | 231 | config COMMON_CLK_S2MPS11 |
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| 198 | 232 | tristate "Clock driver for S2MPS1X/S5M8767 MFD" |
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| 199 | 233 | depends on MFD_SEC_CORE || COMPILE_TEST |
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| 200 | | - ---help--- |
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| 234 | + help |
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| 201 | 235 | This driver supports S2MPS11/S2MPS14/S5M8767 crystal oscillator |
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| 202 | 236 | clock. These multi-function devices have two (S2MPS14) or three |
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| 203 | 237 | (S2MPS11, S5M8767) fixed-rate oscillators, clocked at 32KHz each. |
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| .. | .. |
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| 205 | 239 | config CLK_TWL6040 |
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| 206 | 240 | tristate "External McPDM functional clock from twl6040" |
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| 207 | 241 | depends on TWL6040_CORE |
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| 208 | | - ---help--- |
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| 242 | + help |
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| 209 | 243 | Enable the external functional clock support on OMAP4+ platforms for |
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| 210 | 244 | McPDM. McPDM module is using the external bit clock on the McPDM bus |
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| 211 | 245 | as functional clock. |
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| .. | .. |
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| 214 | 248 | tristate "AXI clkgen driver" |
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| 215 | 249 | depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST |
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| 216 | 250 | help |
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| 217 | | - ---help--- |
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| 218 | 251 | Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx |
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| 219 | 252 | FPGAs. It is commonly used in Analog Devices' reference designs. |
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| 220 | 253 | |
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| 221 | 254 | config CLK_QORIQ |
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| 222 | 255 | bool "Clock driver for Freescale QorIQ platforms" |
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| 223 | 256 | depends on (PPC_E500MC || ARM || ARM64 || COMPILE_TEST) && OF |
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| 224 | | - ---help--- |
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| 257 | + help |
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| 225 | 258 | This adds the clock driver support for Freescale QorIQ platforms |
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| 226 | 259 | using common clock framework. |
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| 227 | 260 | |
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| 261 | +config CLK_LS1028A_PLLDIG |
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| 262 | + tristate "Clock driver for LS1028A Display output" |
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| 263 | + depends on ARCH_LAYERSCAPE || COMPILE_TEST |
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| 264 | + default ARCH_LAYERSCAPE |
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| 265 | + help |
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| 266 | + This driver support the Display output interfaces(LCD, DPHY) pixel clocks |
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| 267 | + of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all |
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| 268 | + features of the PLL are currently supported by the driver. By default, |
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| 269 | + configured bypass mode with this PLL. |
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| 270 | + |
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| 228 | 271 | config COMMON_CLK_XGENE |
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| 229 | 272 | bool "Clock driver for APM XGene SoC" |
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| 230 | | - default y |
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| 273 | + default ARCH_XGENE |
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| 231 | 274 | depends on ARM64 || COMPILE_TEST |
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| 232 | | - ---help--- |
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| 233 | | - Sypport for the APM X-Gene SoC reference, PLL, and device clocks. |
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| 275 | + help |
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| 276 | + Support for the APM X-Gene SoC reference, PLL, and device clocks. |
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| 277 | + |
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| 278 | +config COMMON_CLK_LOCHNAGAR |
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| 279 | + tristate "Cirrus Logic Lochnagar clock driver" |
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| 280 | + depends on MFD_LOCHNAGAR |
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| 281 | + help |
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| 282 | + This driver supports the clocking features of the Cirrus Logic |
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| 283 | + Lochnagar audio development board. |
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| 234 | 284 | |
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| 235 | 285 | config COMMON_CLK_NXP |
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| 236 | 286 | def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) |
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| 237 | 287 | select REGMAP_MMIO if ARCH_LPC32XX |
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| 238 | 288 | select MFD_SYSCON if ARCH_LPC18XX |
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| 239 | | - ---help--- |
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| 289 | + help |
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| 240 | 290 | Support for clock providers on NXP platforms. |
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| 241 | 291 | |
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| 242 | 292 | config COMMON_CLK_PALMAS |
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| 243 | 293 | tristate "Clock driver for TI Palmas devices" |
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| 244 | 294 | depends on MFD_PALMAS |
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| 245 | | - ---help--- |
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| 295 | + help |
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| 246 | 296 | This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO |
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| 247 | 297 | using common clock framework. |
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| 248 | 298 | |
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| 249 | 299 | config COMMON_CLK_PWM |
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| 250 | 300 | tristate "Clock driver for PWMs used as clock outputs" |
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| 251 | 301 | depends on PWM |
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| 252 | | - ---help--- |
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| 302 | + help |
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| 253 | 303 | Adapter driver so that any PWM output can be (mis)used as clock signal |
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| 254 | 304 | at 50% duty cycle. |
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| 255 | 305 | |
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| 256 | 306 | config COMMON_CLK_PXA |
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| 257 | 307 | def_bool COMMON_CLK && ARCH_PXA |
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| 258 | | - ---help--- |
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| 308 | + help |
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| 259 | 309 | Support for the Marvell PXA SoC. |
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| 260 | 310 | |
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| 261 | 311 | config COMMON_CLK_PIC32 |
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| .. | .. |
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| 265 | 315 | bool "Clock driver for the OXNAS SoC Family" |
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| 266 | 316 | depends on ARCH_OXNAS || COMPILE_TEST |
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| 267 | 317 | select MFD_SYSCON |
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| 268 | | - ---help--- |
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| 318 | + help |
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| 269 | 319 | Support for the OXNAS SoC Family clocks. |
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| 270 | 320 | |
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| 271 | 321 | config COMMON_CLK_VC5 |
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| .. | .. |
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| 274 | 324 | depends on OF |
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| 275 | 325 | select REGMAP_I2C |
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| 276 | 326 | help |
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| 277 | | - ---help--- |
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| 278 | 327 | This driver supports the IDT VersaClock 5 and VersaClock 6 |
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| 279 | 328 | programmable clock generators. |
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| 280 | 329 | |
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| 281 | 330 | config COMMON_CLK_STM32MP157 |
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| 282 | 331 | def_bool COMMON_CLK && MACH_STM32MP157 |
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| 283 | 332 | help |
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| 284 | | - ---help--- |
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| 285 | 333 | Support for stm32mp157 SoC family clocks |
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| 286 | 334 | |
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| 287 | 335 | config COMMON_CLK_STM32F |
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| 288 | 336 | def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746) |
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| 289 | 337 | help |
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| 290 | | - ---help--- |
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| 291 | 338 | Support for stm32f4 and stm32f7 SoC families clocks |
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| 292 | 339 | |
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| 293 | 340 | config COMMON_CLK_STM32H7 |
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| 294 | 341 | def_bool COMMON_CLK && MACH_STM32H743 |
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| 295 | 342 | help |
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| 296 | | - ---help--- |
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| 297 | 343 | Support for stm32h7 SoC family clocks |
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| 298 | 344 | |
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| 345 | +config COMMON_CLK_MMP2 |
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| 346 | + def_bool COMMON_CLK && (MACH_MMP2_DT || MACH_MMP3_DT) |
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| 347 | + help |
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| 348 | + Support for Marvell MMP2 and MMP3 SoC clocks |
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| 349 | + |
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| 350 | +config COMMON_CLK_MMP2_AUDIO |
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| 351 | + tristate "Clock driver for MMP2 Audio subsystem" |
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| 352 | + depends on COMMON_CLK_MMP2 || COMPILE_TEST |
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| 353 | + help |
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| 354 | + This driver supports clocks for Audio subsystem on MMP2 SoC. |
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| 355 | + |
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| 356 | +config COMMON_CLK_BD718XX |
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| 357 | + tristate "Clock driver for 32K clk gates on ROHM PMICs" |
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| 358 | + depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828 |
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| 359 | + help |
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| 360 | + This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and |
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| 361 | + ROHM BD70528 PMICs clock gates. |
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| 362 | + |
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| 363 | +config COMMON_CLK_FIXED_MMIO |
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| 364 | + bool "Clock driver for Memory Mapped Fixed values" |
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| 365 | + depends on COMMON_CLK && OF |
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| 366 | + depends on HAS_IOMEM |
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| 367 | + help |
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| 368 | + Support for Memory Mapped IO Fixed clocks |
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| 369 | + |
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| 299 | 370 | source "drivers/clk/actions/Kconfig" |
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| 371 | +source "drivers/clk/analogbits/Kconfig" |
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| 372 | +source "drivers/clk/baikal-t1/Kconfig" |
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| 300 | 373 | source "drivers/clk/bcm/Kconfig" |
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| 301 | 374 | source "drivers/clk/hisilicon/Kconfig" |
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| 302 | 375 | source "drivers/clk/imgtec/Kconfig" |
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| 376 | +source "drivers/clk/imx/Kconfig" |
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| 377 | +source "drivers/clk/ingenic/Kconfig" |
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| 303 | 378 | source "drivers/clk/keystone/Kconfig" |
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| 304 | 379 | source "drivers/clk/mediatek/Kconfig" |
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| 305 | 380 | source "drivers/clk/meson/Kconfig" |
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| .. | .. |
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| 308 | 383 | source "drivers/clk/renesas/Kconfig" |
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| 309 | 384 | source "drivers/clk/rockchip/Kconfig" |
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| 310 | 385 | source "drivers/clk/samsung/Kconfig" |
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| 386 | +source "drivers/clk/sifive/Kconfig" |
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| 311 | 387 | source "drivers/clk/sprd/Kconfig" |
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| 388 | +source "drivers/clk/sunxi/Kconfig" |
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| 312 | 389 | source "drivers/clk/sunxi-ng/Kconfig" |
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| 313 | 390 | source "drivers/clk/tegra/Kconfig" |
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| 314 | 391 | source "drivers/clk/ti/Kconfig" |
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| 315 | 392 | source "drivers/clk/uniphier/Kconfig" |
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| 393 | +source "drivers/clk/x86/Kconfig" |
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| 394 | +source "drivers/clk/zynqmp/Kconfig" |
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| 316 | 395 | |
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| 317 | | -endmenu |
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| 396 | +endif |
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