write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/x86/kvm/i8254.c
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@@ -295,12 +295,24 @@
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 	if (atomic_read(&ps->reinject) == reinject)
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 		return;
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+	/*
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+	 * AMD SVM AVIC accelerates EOI write and does not trap.
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+	 * This cause in-kernel PIT re-inject mode to fail
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+	 * since it checks ps->irq_ack before kvm_set_irq()
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+	 * and relies on the ack notifier to timely queue
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+	 * the pt->worker work iterm and reinject the missed tick.
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+	 * So, deactivate APICv when PIT is in reinject mode.
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+	 */
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 	if (reinject) {
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+		kvm_request_apicv_update(kvm, false,
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+					 APICV_INHIBIT_REASON_PIT_REINJ);
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 		/* The initial state is preserved while ps->reinject == 0. */
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 		kvm_pit_reset_reinject(pit);
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 		kvm_register_irq_ack_notifier(kvm, &ps->irq_ack_notifier);
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 		kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
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 	} else {
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+		kvm_request_apicv_update(kvm, true,
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+					 APICV_INHIBIT_REASON_PIT_REINJ);
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 		kvm_unregister_irq_ack_notifier(kvm, &ps->irq_ack_notifier);
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 		kvm_unregister_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
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 	}
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@@ -355,7 +367,7 @@
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 {
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 	struct kvm_kpit_state *ps = &pit->pit_state;
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-	pr_debug("load_count val is %d, channel is %d\n", val, channel);
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+	pr_debug("load_count val is %u, channel is %d\n", val, channel);
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 	/*
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 	 * The largest possible initial count is 0; this is equivalent
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@@ -450,7 +462,6 @@
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 		if (channel == 3) {
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 			/* Read-Back Command. */
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 			for (channel = 0; channel < 3; channel++) {
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-				s = &pit_state->channels[channel];
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 				if (val & (2 << channel)) {
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 					if (!(val & 0x20))
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 						pit_latch_count(pit, channel);
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@@ -653,7 +664,7 @@
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 	pid_t pid_nr;
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 	int ret;
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-	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
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+	pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL_ACCOUNT);
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 	if (!pit)
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 		return NULL;
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