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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/x86/include/asm/mwait.h
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@@ -20,8 +20,10 @@
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 #define MWAIT_ECX_INTERRUPT_BREAK	0x1
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 #define MWAITX_ECX_TIMER_ENABLE		BIT(1)
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-#define MWAITX_MAX_LOOPS		((u32)-1)
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+#define MWAITX_MAX_WAIT_CYCLES		UINT_MAX
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 #define MWAITX_DISABLE_CSTATES		0xf0
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+#define TPAUSE_C01_STATE		1
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+#define TPAUSE_C02_STATE		0
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 static inline void __monitor(const void *eax, unsigned long ecx,
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 			     unsigned long edx)
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@@ -87,8 +89,6 @@
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 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
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 {
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 	mds_idle_clear_cpu_buffers();
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-
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-	trace_hardirqs_on();
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 	/* "mwait %eax, %ecx;" */
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 	asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
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 		     :: "a" (eax), "c" (ecx));
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@@ -120,4 +120,24 @@
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 	current_clr_polling();
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 }
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+/*
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+ * Caller can specify whether to enter C0.1 (low latency, less
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+ * power saving) or C0.2 state (saves more power, but longer wakeup
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+ * latency). This may be overridden by the IA32_UMWAIT_CONTROL MSR
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+ * which can force requests for C0.2 to be downgraded to C0.1.
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+ */
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+static inline void __tpause(u32 ecx, u32 edx, u32 eax)
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+{
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+	/* "tpause %ecx, %edx, %eax;" */
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+	#ifdef CONFIG_AS_TPAUSE
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+	asm volatile("tpause %%ecx\n"
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+		     :
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+		     : "c"(ecx), "d"(edx), "a"(eax));
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+	#else
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+	asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1\t\n"
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+		     :
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+		     : "c"(ecx), "d"(edx), "a"(eax));
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+	#endif
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+}
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+
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 #endif /* _ASM_X86_MWAIT_H */