write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/x86/include/asm/msr-index.h
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@@ -54,8 +54,13 @@
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 #define SPEC_CTRL_RRSBA_DIS_S_SHIFT	6	   /* Disable RRSBA behavior */
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 #define SPEC_CTRL_RRSBA_DIS_S		BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
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+/* A mask for bits which the kernel toggles when controlling mitigations */
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+#define SPEC_CTRL_MITIGATIONS_MASK	(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
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+							| SPEC_CTRL_RRSBA_DIS_S)
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+
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 #define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
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 #define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
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+#define PRED_CMD_SBPB			BIT(7)	   /* Selective Branch Prediction Barrier */
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 #define MSR_PPIN_CTL			0x0000004e
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 #define MSR_PPIN			0x0000004f
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@@ -152,6 +157,15 @@
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 						 * Not susceptible to Post-Barrier
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 						 * Return Stack Buffer Predictions.
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 						 */
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+#define ARCH_CAP_GDS_CTRL		BIT(25)	/*
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+						 * CPU is vulnerable to Gather
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+						 * Data Sampling (GDS) and
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+						 * has controls for mitigation.
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+						 */
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+#define ARCH_CAP_GDS_NO			BIT(26)	/*
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+						 * CPU is not vulnerable to Gather
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+						 * Data Sampling (GDS).
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+						 */
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 #define MSR_IA32_FLUSH_CMD		0x0000010b
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 #define L1D_FLUSH			BIT(0)	/*
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@@ -170,6 +184,8 @@
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 #define MSR_IA32_MCU_OPT_CTRL		0x00000123
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 #define RNGDS_MITG_DIS			BIT(0)
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 #define FB_CLEAR_DIS			BIT(3)	/* CPU Fill buffer clear disable */
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+#define GDS_MITG_DIS			BIT(4)	/* Disable GDS mitigation */
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+#define GDS_MITG_LOCKED			BIT(5)	/* GDS mitigation locked */
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 #define MSR_IA32_SYSENTER_CS		0x00000174
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 #define MSR_IA32_SYSENTER_ESP		0x00000175
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@@ -493,6 +509,7 @@
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 #define MSR_AMD64_DE_CFG		0xc0011029
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 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT	 1
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 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE	BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
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+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
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 #define MSR_AMD64_BU_CFG2		0xc001102a
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 #define MSR_AMD64_IBSFETCHCTL		0xc0011030
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@@ -514,6 +531,7 @@
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 #define MSR_AMD64_ICIBSEXTDCTL		0xc001103c
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 #define MSR_AMD64_IBSOPDATA4		0xc001103d
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 #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
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+#define MSR_AMD64_VM_PAGE_FLUSH		0xc001011e
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 #define MSR_AMD64_SEV_ES_GHCB		0xc0010130
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 #define MSR_AMD64_SEV			0xc0010131
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 #define MSR_AMD64_SEV_ENABLED_BIT	0