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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/arch/x86/include/asm/cpu_entry_area.h
....@@ -1,4 +1,4 @@
1
-// SPDX-License-Identifier: GPL-2.0
1
+/* SPDX-License-Identifier: GPL-2.0 */
22 
33 #ifndef _ASM_X86_CPU_ENTRY_AREA_H
44 #define _ASM_X86_CPU_ENTRY_AREA_H
....@@ -6,6 +6,78 @@
66 #include <linux/percpu-defs.h>
77 #include <asm/processor.h>
88 #include <asm/intel_ds.h>
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+#include <asm/pgtable_areas.h>
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+
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+#ifdef CONFIG_X86_64
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+
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+#ifdef CONFIG_AMD_MEM_ENCRYPT
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+#define VC_EXCEPTION_STKSZ	EXCEPTION_STKSZ
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+#else
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+#define VC_EXCEPTION_STKSZ	0
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+#endif
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+
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+/* Macro to enforce the same ordering and stack sizes */
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+#define ESTACKS_MEMBERS(guardsize, optional_stack_size)		\
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+	char	DF_stack_guard[guardsize];			\
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+	char	DF_stack[EXCEPTION_STKSZ];			\
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+	char	NMI_stack_guard[guardsize];			\
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+	char	NMI_stack[EXCEPTION_STKSZ];			\
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+	char	DB_stack_guard[guardsize];			\
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+	char	DB_stack[EXCEPTION_STKSZ];			\
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+	char	MCE_stack_guard[guardsize];			\
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+	char	MCE_stack[EXCEPTION_STKSZ];			\
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+	char	VC_stack_guard[guardsize];			\
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+	char	VC_stack[optional_stack_size];			\
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+	char	VC2_stack_guard[guardsize];			\
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+	char	VC2_stack[optional_stack_size];			\
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+	char	IST_top_guard[guardsize];			\
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+
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+/* The exception stacks' physical storage. No guard pages required */
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+struct exception_stacks {
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+	ESTACKS_MEMBERS(0, VC_EXCEPTION_STKSZ)
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+};
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+
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+/* The effective cpu entry area mapping with guard pages. */
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+struct cea_exception_stacks {
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+	ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ)
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+};
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+
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+/*
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+ * The exception stack ordering in [cea_]exception_stacks
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+ */
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+enum exception_stack_ordering {
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+	ESTACK_DF,
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+	ESTACK_NMI,
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+	ESTACK_DB,
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+	ESTACK_MCE,
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+	ESTACK_VC,
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+	ESTACK_VC2,
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+	N_EXCEPTION_STACKS
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+};
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+
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+#define CEA_ESTACK_SIZE(st)					\
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+	sizeof(((struct cea_exception_stacks *)0)->st## _stack)
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+
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+#define CEA_ESTACK_BOT(ceastp, st)				\
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+	((unsigned long)&(ceastp)->st## _stack)
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+
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+#define CEA_ESTACK_TOP(ceastp, st)				\
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+	(CEA_ESTACK_BOT(ceastp, st) + CEA_ESTACK_SIZE(st))
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+
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+#define CEA_ESTACK_OFFS(st)					\
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+	offsetof(struct cea_exception_stacks, st## _stack)
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+
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+#define CEA_ESTACK_PAGES					\
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+	(sizeof(struct cea_exception_stacks) / PAGE_SIZE)
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+
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+#endif
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+
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+#ifdef CONFIG_X86_32
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+struct doublefault_stack {
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+	unsigned long stack[(PAGE_SIZE - sizeof(struct x86_hw_tss)) / sizeof(unsigned long)];
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+	struct x86_hw_tss tss;
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+} __aligned(PAGE_SIZE);
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+#endif
981 
1082 /*
1183  * cpu_entry_area is a percpu region that contains things needed by the CPU
....@@ -20,9 +92,18 @@
2092 
2193 	/*
2294 	 * The GDT is just below entry_stack and thus serves (on x86_64) as
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-	 * a a read-only guard page.
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+	 * a read-only guard page. On 32-bit the GDT must be writeable, so
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+	 * it needs an extra guard page.
2497 	 */
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+#ifdef CONFIG_X86_32
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+	char guard_entry_stack[PAGE_SIZE];
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+#endif
25101 	struct entry_stack_page entry_stack_page;
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+
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+#ifdef CONFIG_X86_32
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+	char guard_doublefault_stack[PAGE_SIZE];
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+	struct doublefault_stack doublefault_stack;
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+#endif
26107 
27108 	/*
28109 	 * On x86_64, the TSS is mapped RO.  On x86_32, it's mapped RW because
....@@ -30,18 +111,12 @@
30111 	 */
31112 	struct tss_struct tss;
32113 
33
-	char entry_trampoline[PAGE_SIZE];
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-
35114 #ifdef CONFIG_X86_64
36115 	/*
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-	 * Exception stacks used for IST entries.
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-	 *
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-	 * In the future, this should have a separate slot for each stack
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-	 * with guard pages between them.
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+	 * Exception stacks used for IST entries with guard pages.
41117 	 */
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-	char exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ];
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+	struct cea_exception_stacks estacks;
43119 #endif
44
-#ifdef CONFIG_CPU_SUP_INTEL
45120 	/*
46121 	 * Per CPU debug store for Intel performance monitoring. Wastes a
47122 	 * full page at the moment.
....@@ -52,24 +127,19 @@
52127 	 * Reserve enough fixmap PTEs.
53128 	 */
54129 	struct debug_store_buffers cpu_debug_buffers;
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-#endif
56130 };
57131 
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-#define CPU_ENTRY_AREA_SIZE	(sizeof(struct cpu_entry_area))
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-#define CPU_ENTRY_AREA_TOT_SIZE	(CPU_ENTRY_AREA_SIZE * NR_CPUS)
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+#define CPU_ENTRY_AREA_SIZE		(sizeof(struct cpu_entry_area))
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+#define CPU_ENTRY_AREA_ARRAY_SIZE	(CPU_ENTRY_AREA_SIZE * NR_CPUS)
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+
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+/* Total size includes the readonly IDT mapping page as well: */
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+#define CPU_ENTRY_AREA_TOTAL_SIZE	(CPU_ENTRY_AREA_ARRAY_SIZE + PAGE_SIZE)
60137 
61138 DECLARE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
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+DECLARE_PER_CPU(struct cea_exception_stacks *, cea_exception_stacks);
62140 
63141 extern void setup_cpu_entry_areas(void);
64142 extern void cea_set_pte(void *cea_vaddr, phys_addr_t pa, pgprot_t flags);
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-
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-#define	CPU_ENTRY_AREA_RO_IDT		CPU_ENTRY_AREA_BASE
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-#define CPU_ENTRY_AREA_PER_CPU		(CPU_ENTRY_AREA_RO_IDT + PAGE_SIZE)
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-
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-#define CPU_ENTRY_AREA_RO_IDT_VADDR	((void *)CPU_ENTRY_AREA_RO_IDT)
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-
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-#define CPU_ENTRY_AREA_MAP_SIZE			\
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-	(CPU_ENTRY_AREA_PER_CPU + CPU_ENTRY_AREA_TOT_SIZE - CPU_ENTRY_AREA_BASE)
73143 
74144 extern struct cpu_entry_area *get_cpu_entry_area(int cpu);
75145 
....@@ -78,4 +148,10 @@
78148 	return &get_cpu_entry_area(cpu)->entry_stack_page.stack;
79149 }
80150 
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+#define __this_cpu_ist_top_va(name)					\
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+	CEA_ESTACK_TOP(__this_cpu_read(cea_exception_stacks), name)
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+
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+#define __this_cpu_ist_bottom_va(name)					\
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+	CEA_ESTACK_BOT(__this_cpu_read(cea_exception_stacks), name)
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+
81157 #endif