write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/sparc/kernel/pci_sun4v.c
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@@ -16,6 +16,7 @@
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 #include <linux/export.h>
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 #include <linux/log2.h>
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 #include <linux/of_device.h>
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+#include <linux/dma-map-ops.h>
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 #include <asm/iommu-common.h>
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 #include <asm/iommu.h>
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@@ -73,6 +74,11 @@
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 	p->npages	= 0;
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 }
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+static inline bool iommu_use_atu(struct iommu *iommu, u64 mask)
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+{
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+	return iommu->atu && mask > DMA_BIT_MASK(32);
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+}
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+
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 /* Interrupts must be disabled.  */
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 static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
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 {
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@@ -92,7 +98,7 @@
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 		prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
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 	while (npages != 0) {
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-		if (mask <= DMA_BIT_MASK(32)) {
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+		if (!iommu_use_atu(pbm->iommu, mask)) {
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 			num = pci_sun4v_iommu_map(devhandle,
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 						  HV_PCI_TSBID(0, entry),
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 						  npages,
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@@ -179,7 +185,6 @@
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 	unsigned long flags, order, first_page, npages, n;
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 	unsigned long prot = 0;
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 	struct iommu *iommu;
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-	struct atu *atu;
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 	struct iommu_map_table *tbl;
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 	struct page *page;
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 	void *ret;
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@@ -205,13 +210,11 @@
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 	memset((char *)first_page, 0, PAGE_SIZE << order);
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 	iommu = dev->archdata.iommu;
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-	atu = iommu->atu;
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-
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 	mask = dev->coherent_dma_mask;
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-	if (mask <= DMA_BIT_MASK(32))
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+	if (!iommu_use_atu(iommu, mask))
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 		tbl = &iommu->tbl;
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 	else
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-		tbl = &atu->tbl;
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+		tbl = &iommu->atu->tbl;
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 	entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
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 				      (unsigned long)(-1), 0);
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@@ -333,7 +336,7 @@
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 	atu = iommu->atu;
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 	devhandle = pbm->devhandle;
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-	if (dvma <= DMA_BIT_MASK(32)) {
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+	if (!iommu_use_atu(iommu, dvma)) {
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 		tbl = &iommu->tbl;
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 		iotsb_num = 0; /* we don't care for legacy iommu */
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 	} else {
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@@ -374,7 +377,7 @@
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 	npages >>= IO_PAGE_SHIFT;
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 	mask = *dev->dma_mask;
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-	if (mask <= DMA_BIT_MASK(32))
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+	if (!iommu_use_atu(iommu, mask))
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 		tbl = &iommu->tbl;
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 	else
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 		tbl = &atu->tbl;
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@@ -414,12 +417,12 @@
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 bad:
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 	if (printk_ratelimit())
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 		WARN_ON(1);
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-	return SPARC_MAPPING_ERROR;
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+	return DMA_MAPPING_ERROR;
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 iommu_map_fail:
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 	local_irq_restore(flags);
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 	iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
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-	return SPARC_MAPPING_ERROR;
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+	return DMA_MAPPING_ERROR;
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 }
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 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
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@@ -506,11 +509,10 @@
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 	iommu_batch_start(dev, prot, ~0UL);
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 	max_seg_size = dma_get_max_seg_size(dev);
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-	seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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-				  IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
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+	seg_boundary_size = dma_get_seg_boundary_nr_pages(dev, IO_PAGE_SHIFT);
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 	mask = *dev->dma_mask;
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-	if (mask <= DMA_BIT_MASK(32))
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+	if (!iommu_use_atu(iommu, mask))
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 		tbl = &iommu->tbl;
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 	else
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 		tbl = &atu->tbl;
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@@ -592,7 +594,7 @@
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 	if (outcount < incount) {
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 		outs = sg_next(outs);
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-		outs->dma_address = SPARC_MAPPING_ERROR;
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+		outs->dma_address = DMA_MAPPING_ERROR;
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 		outs->dma_length = 0;
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 	}
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@@ -609,7 +611,7 @@
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 			iommu_tbl_range_free(tbl, vaddr, npages,
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 					     IOMMU_ERROR_CODE);
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 			/* XXX demap? XXX */
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-			s->dma_address = SPARC_MAPPING_ERROR;
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+			s->dma_address = DMA_MAPPING_ERROR;
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 			s->dma_length = 0;
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 		}
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 		if (s == outs)
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@@ -674,23 +676,12 @@
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 static int dma_4v_supported(struct device *dev, u64 device_mask)
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 {
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 	struct iommu *iommu = dev->archdata.iommu;
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-	u64 dma_addr_mask = iommu->dma_addr_mask;
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-	if (device_mask > DMA_BIT_MASK(32)) {
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-		if (iommu->atu)
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-			dma_addr_mask = iommu->atu->dma_addr_mask;
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-		else
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-			return 0;
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-	}
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-
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-	if ((device_mask & dma_addr_mask) == dma_addr_mask)
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+	if (ali_sound_dma_hack(dev, device_mask))
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 		return 1;
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-	return pci64_dma_supported(to_pci_dev(dev), device_mask);
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-}
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-
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-static int dma_4v_mapping_error(struct device *dev, dma_addr_t dma_addr)
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-{
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-	return dma_addr == SPARC_MAPPING_ERROR;
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+	if (device_mask < iommu->dma_addr_mask)
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+		return 0;
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+	return 1;
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 }
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 static const struct dma_map_ops sun4v_dma_ops = {
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@@ -701,7 +692,6 @@
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 	.map_sg				= dma_4v_map_sg,
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 	.unmap_sg			= dma_4v_unmap_sg,
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 	.dma_supported			= dma_4v_supported,
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-	.mapping_error			= dma_4v_mapping_error,
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 };
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 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)