write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/powerpc/sysdev/fsl_pci.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * MPC83xx/85xx/86xx PCI/PCIE support routing.
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  *
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@@ -11,11 +12,6 @@
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  * MPC83xx PCI-Express support:
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  * 	Tony Li <tony.li@freescale.com>
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  * 	Anton Vorontsov <avorontsov@ru.mvista.com>
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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 #include <linux/kernel.h>
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 #include <linux/pci.h>
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@@ -40,6 +36,7 @@
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 #include <asm/mpc85xx.h>
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 #include <asm/disassemble.h>
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 #include <asm/ppc-opcode.h>
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+#include <asm/swiotlb.h>
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 #include <sysdev/fsl_soc.h>
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 #include <sysdev/fsl_pci.h>
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@@ -114,33 +111,33 @@
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 static u64 pci64_dma_offset;
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 #ifdef CONFIG_SWIOTLB
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+static void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev)
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+{
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+	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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+
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+	pdev->dev.bus_dma_limit =
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+		hose->dma_window_base_cur + hose->dma_window_size - 1;
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+}
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+
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 static void setup_swiotlb_ops(struct pci_controller *hose)
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 {
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-	if (ppc_swiotlb_enable) {
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+	if (ppc_swiotlb_enable)
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 		hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
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-		set_pci_dma_ops(&powerpc_swiotlb_dma_ops);
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-	}
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 }
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 #else
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 static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
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 #endif
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-static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
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+static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
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 {
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-	if (!dev->dma_mask || !dma_supported(dev, dma_mask))
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-		return -EIO;
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-
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 	/*
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 	 * Fix up PCI devices that are able to DMA to the large inbound
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 	 * mapping that allows addressing any RAM address from across PCI.
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 	 */
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 	if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
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-		set_dma_ops(dev, &dma_nommu_ops);
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-		set_dma_offset(dev, pci64_dma_offset);
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+		dev->bus_dma_limit = 0;
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+		dev->archdata.dma_offset = pci64_dma_offset;
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 	}
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-
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-	*dev->dma_mask = dma_mask;
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-	return 0;
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 }
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 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
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@@ -523,6 +520,7 @@
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 	struct resource rsrc;
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 	const int *bus_range;
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 	u8 hdr_type, progif;
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+	u32 class_code;
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 	struct device_node *dev;
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 	struct ccsr_pci __iomem *pci;
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 	u16 temp;
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@@ -596,6 +594,13 @@
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 			PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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 		if (fsl_pcie_check_link(hose))
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 			hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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+		/* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
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+		if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
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+			early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
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+			class_code &= 0xff;
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+			class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
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+			early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
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+		}
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 	} else {
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 		/*
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 		 * Set PBFR(PCI Bus Function Register)[10] = 1 to
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@@ -1068,13 +1073,11 @@
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 	addr += mfspr(SPRN_MCAR);
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 	if (is_in_pci_mem_space(addr)) {
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-		if (user_mode(regs)) {
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-			pagefault_disable();
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-			ret = get_user(inst, (__u32 __user *)regs->nip);
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-			pagefault_enable();
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-		} else {
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-			ret = probe_kernel_address((void *)regs->nip, inst);
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-		}
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+		if (user_mode(regs))
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+			ret = copy_from_user_nofault(&inst,
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+					(void __user *)regs->nip, sizeof(inst));
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+		else
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+			ret = get_kernel_nofault(inst, (void *)regs->nip);
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 		if (!ret && mcheck_handle_load(regs, inst)) {
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 			regs->nip += 4;