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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/arch/powerpc/platforms/powermac/sleep.S
....@@ -1,13 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * This file contains sleep low-level functions for PowerBook G3.
34  *    Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
45  *    and Paul Mackerras (paulus@samba.org).
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License
8
- * as published by the Free Software Foundation; either version
9
- * 2 of the License, or (at your option) any later version.
10
- *
116  */
127 
138 #include <asm/processor.h>
....@@ -49,7 +44,8 @@
4944 #define SL_TB		0xa0
5045 #define SL_R2		0xa8
5146 #define SL_CR		0xac
52
-#define SL_R12		0xb0	/* r12 to r31 */
47
+#define SL_LR		0xb0
48
+#define SL_R12		0xb4	/* r12 to r31 */
5349 #define SL_SIZE		(SL_R12 + 80)
5450 
5551 	.section .text
....@@ -64,109 +60,111 @@
6460  * vector that will be called by the ROM on wakeup
6561  */
6662 _GLOBAL(low_sleep_handler)
67
-#ifndef CONFIG_6xx
63
+#ifndef CONFIG_PPC_BOOK3S_32
6864 	blr
6965 #else
7066 	mflr	r0
71
-	stw	r0,4(r1)
72
-	stwu	r1,-SL_SIZE(r1)
67
+	lis	r11,sleep_storage@ha
68
+	addi	r11,r11,sleep_storage@l
69
+	stw	r0,SL_LR(r11)
7370 	mfcr	r0
74
-	stw	r0,SL_CR(r1)
75
-	stw	r2,SL_R2(r1)
76
-	stmw	r12,SL_R12(r1)
71
+	stw	r0,SL_CR(r11)
72
+	stw	r1,SL_SP(r11)
73
+	stw	r2,SL_R2(r11)
74
+	stmw	r12,SL_R12(r11)
7775 
7876 	/* Save MSR & SDR1 */
7977 	mfmsr	r4
80
-	stw	r4,SL_MSR(r1)
78
+	stw	r4,SL_MSR(r11)
8179 	mfsdr1	r4
82
-	stw	r4,SL_SDR1(r1)
80
+	stw	r4,SL_SDR1(r11)
8381 
8482 	/* Get a stable timebase and save it */
8583 1:	mftbu	r4
86
-	stw	r4,SL_TB(r1)
84
+	stw	r4,SL_TB(r11)
8785 	mftb	r5
88
-	stw	r5,SL_TB+4(r1)
86
+	stw	r5,SL_TB+4(r11)
8987 	mftbu	r3
9088 	cmpw	r3,r4
9189 	bne	1b
9290 
9391 	/* Save SPRGs */
9492 	mfsprg	r4,0
95
-	stw	r4,SL_SPRG0(r1)
93
+	stw	r4,SL_SPRG0(r11)
9694 	mfsprg	r4,1
97
-	stw	r4,SL_SPRG0+4(r1)
95
+	stw	r4,SL_SPRG0+4(r11)
9896 	mfsprg	r4,2
99
-	stw	r4,SL_SPRG0+8(r1)
97
+	stw	r4,SL_SPRG0+8(r11)
10098 	mfsprg	r4,3
101
-	stw	r4,SL_SPRG0+12(r1)
99
+	stw	r4,SL_SPRG0+12(r11)
102100 
103101 	/* Save BATs */
104102 	mfdbatu	r4,0
105
-	stw	r4,SL_DBAT0(r1)
103
+	stw	r4,SL_DBAT0(r11)
106104 	mfdbatl	r4,0
107
-	stw	r4,SL_DBAT0+4(r1)
105
+	stw	r4,SL_DBAT0+4(r11)
108106 	mfdbatu	r4,1
109
-	stw	r4,SL_DBAT1(r1)
107
+	stw	r4,SL_DBAT1(r11)
110108 	mfdbatl	r4,1
111
-	stw	r4,SL_DBAT1+4(r1)
109
+	stw	r4,SL_DBAT1+4(r11)
112110 	mfdbatu	r4,2
113
-	stw	r4,SL_DBAT2(r1)
111
+	stw	r4,SL_DBAT2(r11)
114112 	mfdbatl	r4,2
115
-	stw	r4,SL_DBAT2+4(r1)
113
+	stw	r4,SL_DBAT2+4(r11)
116114 	mfdbatu	r4,3
117
-	stw	r4,SL_DBAT3(r1)
115
+	stw	r4,SL_DBAT3(r11)
118116 	mfdbatl	r4,3
119
-	stw	r4,SL_DBAT3+4(r1)
117
+	stw	r4,SL_DBAT3+4(r11)
120118 	mfibatu	r4,0
121
-	stw	r4,SL_IBAT0(r1)
119
+	stw	r4,SL_IBAT0(r11)
122120 	mfibatl	r4,0
123
-	stw	r4,SL_IBAT0+4(r1)
121
+	stw	r4,SL_IBAT0+4(r11)
124122 	mfibatu	r4,1
125
-	stw	r4,SL_IBAT1(r1)
123
+	stw	r4,SL_IBAT1(r11)
126124 	mfibatl	r4,1
127
-	stw	r4,SL_IBAT1+4(r1)
125
+	stw	r4,SL_IBAT1+4(r11)
128126 	mfibatu	r4,2
129
-	stw	r4,SL_IBAT2(r1)
127
+	stw	r4,SL_IBAT2(r11)
130128 	mfibatl	r4,2
131
-	stw	r4,SL_IBAT2+4(r1)
129
+	stw	r4,SL_IBAT2+4(r11)
132130 	mfibatu	r4,3
133
-	stw	r4,SL_IBAT3(r1)
131
+	stw	r4,SL_IBAT3(r11)
134132 	mfibatl	r4,3
135
-	stw	r4,SL_IBAT3+4(r1)
133
+	stw	r4,SL_IBAT3+4(r11)
136134 
137135 BEGIN_MMU_FTR_SECTION
138136 	mfspr	r4,SPRN_DBAT4U
139
-	stw	r4,SL_DBAT4(r1)
137
+	stw	r4,SL_DBAT4(r11)
140138 	mfspr	r4,SPRN_DBAT4L
141
-	stw	r4,SL_DBAT4+4(r1)
139
+	stw	r4,SL_DBAT4+4(r11)
142140 	mfspr	r4,SPRN_DBAT5U
143
-	stw	r4,SL_DBAT5(r1)
141
+	stw	r4,SL_DBAT5(r11)
144142 	mfspr	r4,SPRN_DBAT5L
145
-	stw	r4,SL_DBAT5+4(r1)
143
+	stw	r4,SL_DBAT5+4(r11)
146144 	mfspr	r4,SPRN_DBAT6U
147
-	stw	r4,SL_DBAT6(r1)
145
+	stw	r4,SL_DBAT6(r11)
148146 	mfspr	r4,SPRN_DBAT6L
149
-	stw	r4,SL_DBAT6+4(r1)
147
+	stw	r4,SL_DBAT6+4(r11)
150148 	mfspr	r4,SPRN_DBAT7U
151
-	stw	r4,SL_DBAT7(r1)
149
+	stw	r4,SL_DBAT7(r11)
152150 	mfspr	r4,SPRN_DBAT7L
153
-	stw	r4,SL_DBAT7+4(r1)
151
+	stw	r4,SL_DBAT7+4(r11)
154152 	mfspr	r4,SPRN_IBAT4U
155
-	stw	r4,SL_IBAT4(r1)
153
+	stw	r4,SL_IBAT4(r11)
156154 	mfspr	r4,SPRN_IBAT4L
157
-	stw	r4,SL_IBAT4+4(r1)
155
+	stw	r4,SL_IBAT4+4(r11)
158156 	mfspr	r4,SPRN_IBAT5U
159
-	stw	r4,SL_IBAT5(r1)
157
+	stw	r4,SL_IBAT5(r11)
160158 	mfspr	r4,SPRN_IBAT5L
161
-	stw	r4,SL_IBAT5+4(r1)
159
+	stw	r4,SL_IBAT5+4(r11)
162160 	mfspr	r4,SPRN_IBAT6U
163
-	stw	r4,SL_IBAT6(r1)
161
+	stw	r4,SL_IBAT6(r11)
164162 	mfspr	r4,SPRN_IBAT6L
165
-	stw	r4,SL_IBAT6+4(r1)
163
+	stw	r4,SL_IBAT6+4(r11)
166164 	mfspr	r4,SPRN_IBAT7U
167
-	stw	r4,SL_IBAT7(r1)
165
+	stw	r4,SL_IBAT7(r11)
168166 	mfspr	r4,SPRN_IBAT7L
169
-	stw	r4,SL_IBAT7+4(r1)
167
+	stw	r4,SL_IBAT7+4(r11)
170168 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
171169 
172170 	/* Backup various CPU config stuffs */
....@@ -185,9 +183,9 @@
185183 	lis	r5,grackle_wake_up@ha
186184 	addi	r5,r5,grackle_wake_up@l
187185 	tophys(r5,r5)
188
-	stw	r5,SL_PC(r1)
186
+	stw	r5,SL_PC(r11)
189187 	lis	r4,KERNELBASE@h
190
-	tophys(r5,r1)
188
+	tophys(r5,r11)
191189 	addi	r5,r5,SL_PC
192190 	lis	r6,MAGIC@ha
193191 	addi	r6,r6,MAGIC@l
....@@ -199,15 +197,9 @@
199197 	tophys(r3,r3)
200198 	stw	r3,0x80(r4)
201199 	stw	r5,0x84(r4)
202
-	/* Store a pointer to our backup storage into
203
-	 * a kernel global
204
-	 */
205
-	lis r3,sleep_storage@ha
206
-	addi r3,r3,sleep_storage@l
207
-	stw r5,0(r3)
208200 
209
-	.globl	low_cpu_die
210
-low_cpu_die:
201
+	.globl	low_cpu_offline_self
202
+low_cpu_offline_self:
211203 	/* Flush & disable all caches */
212204 	bl	flush_disable_caches
213205 
....@@ -249,7 +241,7 @@
249241 	mtmsr	r2
250242 	isync
251243 	b	1b
252
-
244
+_ASM_NOKPROBE_SYMBOL(low_cpu_offline_self)
253245 /*
254246  * Here is the resume code.
255247  */
....@@ -284,9 +276,10 @@
284276 	lis	r3,sleep_storage@ha
285277 	addi	r3,r3,sleep_storage@l
286278 	tophys(r3,r3)
287
-	lwz	r1,0(r3)
279
+	addi	r1,r3,SL_PC
288280 
289281 	/* Pass thru to older resume code ... */
282
+_ASM_NOKPROBE_SYMBOL(core99_wake_up)
290283 /*
291284  * Here is the resume code for older machines.
292285  * r1 has the physical address of SL_PC(sp).
....@@ -298,14 +291,7 @@
298291 	 * we do any r1 memory access as we are not sure they
299292 	 * are in a sane state above the first 256Mb region
300293 	 */
301
-	li	r0,16		/* load up segment register values */
302
-	mtctr	r0		/* for context 0 */
303
-	lis	r3,0x2000	/* Ku = 1, VSID = 0 */
304
-	li	r4,0
305
-3:	mtsrin	r3,r4
306
-	addi	r3,r3,0x111	/* increment VSID */
307
-	addis	r4,r4,0x1000	/* address of next segment */
308
-	bdnz	3b
294
+	bl	load_segment_registers
309295 	sync
310296 	isync
311297 
....@@ -410,13 +396,6 @@
410396 	blt	1b
411397 	sync
412398 
413
-	/* restore the MSR and turn on the MMU */
414
-	lwz	r3,SL_MSR(r1)
415
-	bl	turn_on_mmu
416
-
417
-	/* get back the stack pointer */
418
-	tovirt(r1,r1)
419
-
420399 	/* Restore TB */
421400 	li	r3,0
422401 	mttbl	r3
....@@ -430,27 +409,25 @@
430409 	mtcr	r0
431410 	lwz	r2,SL_R2(r1)
432411 	lmw	r12,SL_R12(r1)
433
-	addi	r1,r1,SL_SIZE
434
-	lwz	r0,4(r1)
435
-	mtlr	r0
436
-	blr
437412 
438
-turn_on_mmu:
439
-	mflr	r4
440
-	tovirt(r4,r4)
413
+	/* restore the MSR and SP and turn on the MMU and return */
414
+	lwz	r3,SL_MSR(r1)
415
+	lwz	r4,SL_LR(r1)
416
+	lwz	r1,SL_SP(r1)
441417 	mtsrr0	r4
442418 	mtsrr1	r3
443419 	sync
444420 	isync
445421 	rfi
422
+_ASM_NOKPROBE_SYMBOL(grackle_wake_up)
446423 
447424 #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
448425 
449
-	.section .data
426
+	.section .bss
450427 	.balign	L1_CACHE_BYTES
451428 sleep_storage:
452
-	.long 0
429
+	.space SL_SIZE
453430 	.balign	L1_CACHE_BYTES, 0
454431 
455
-#endif /* CONFIG_6xx */
432
+#endif /* CONFIG_PPC_BOOK3S_32 */
456433 	.section .text