write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/powerpc/perf/power6-pmu.c
..
..
@@ -1,18 +1,16 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
1
2
 /*
2
3
  * Performance counter support for POWER6 processors.
3
4
  *
4
5
  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License
8
- * as published by the Free Software Foundation; either version
9
- * 2 of the License, or (at your option) any later version.
10
6
  */
11
7
 #include <linux/kernel.h>
12
8
 #include <linux/perf_event.h>
13
9
 #include <linux/string.h>
14
10
 #include <asm/reg.h>
15
11
 #include <asm/cputable.h>
12
+
13
+#include "internal.h"
16
14
 
17
15
 /*
18
16
  * Bits in event code for POWER6
..
..
@@ -175,7 +173,7 @@
175
173
  * Assign PMC numbers and compute MMCR1 value for a set of events
176
174
  */
177
175
 static int p6_compute_mmcr(u64 event[], int n_ev,
178
-			   unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
176
+			   unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[])
179
177
 {
180
178
 	unsigned long mmcr1 = 0;
181
179
 	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
..
..
@@ -247,13 +245,13 @@
247
245
 		if (pmc < 4)
248
246
 			mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
249
247
 	}
250
-	mmcr[0] = 0;
248
+	mmcr->mmcr0 = 0;
251
249
 	if (pmc_inuse & 1)
252
-		mmcr[0] = MMCR0_PMC1CE;
250
+		mmcr->mmcr0 = MMCR0_PMC1CE;
253
251
 	if (pmc_inuse & 0xe)
254
-		mmcr[0] |= MMCR0_PMCjCE;
255
-	mmcr[1] = mmcr1;
256
-	mmcr[2] = mmcra;
252
+		mmcr->mmcr0 |= MMCR0_PMCjCE;
253
+	mmcr->mmcr1 = mmcr1;
254
+	mmcr->mmcra = mmcra;
257
255
 	return 0;
258
256
 }
259
257
 
..
..
@@ -461,11 +459,11 @@
461
459
 	return nalt;
462
460
 }
463
461
 
464
-static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[])
462
+static void p6_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
465
463
 {
466
464
 	/* Set PMCxSEL to 0 to disable PMCx */
467
465
 	if (pmc <= 3)
468
-		mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
466
+		mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
469
467
 }
470
468
 
471
469
 static int power6_generic_events[] = {
..
..
@@ -485,7 +483,7 @@
485
483
  * are event codes.
486
484
  * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
487
485
  */
488
-static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
486
+static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
489
487
 	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
490
488
 		[C(OP_READ)] = {	0x280030,	0x80080		},
491
489
 		[C(OP_WRITE)] = {	0x180032,	0x80088		},
..
..
@@ -540,7 +538,7 @@
540
538
 	.cache_events		= &power6_cache_events,
541
539
 };
542
540
 
543
-static int __init init_power6_pmu(void)
541
+int init_power6_pmu(void)
544
542
 {
545
543
 	if (!cur_cpu_spec->oprofile_cpu_type ||
546
544
 	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
..
..
@@ -548,5 +546,3 @@
548
546
 
549
547
 	return register_power_pmu(&power6_pmu);
550
548
 }
551
-
552
-early_initcall(init_power6_pmu);