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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/arch/powerpc/kernel/misc_64.S
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * This file contains miscellaneous low-level functions.
34  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
....@@ -6,12 +7,6 @@
67  * and Paul Mackerras.
78  * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
89  * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
9
- *
10
- * This program is free software; you can redistribute it and/or
11
- * modify it under the terms of the GNU General Public License
12
- * as published by the Free Software Foundation; either version
13
- * 2 of the License, or (at your option) any later version.
14
- *
1510  */
1611 
1712 #include <linux/sys.h>
....@@ -52,160 +47,6 @@
5247 	ld	r1,0(r1)
5348 	ld	r0,16(r1)
5449 	mtlr	r0
55
-	blr
56
-
57
-	.section	".toc","aw"
58
-PPC64_CACHES:
59
-	.tc		ppc64_caches[TC],ppc64_caches
60
-	.section	".text"
61
-
62
-/*
63
- * Write any modified data cache blocks out to memory
64
- * and invalidate the corresponding instruction cache blocks.
65
- *
66
- * flush_icache_range(unsigned long start, unsigned long stop)
67
- *
68
- *   flush all bytes from start through stop-1 inclusive
69
- */
70
-
71
-_GLOBAL_TOC(flush_icache_range)
72
-BEGIN_FTR_SECTION
73
-	PURGE_PREFETCHED_INS
74
-	blr
75
-END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
76
-/*
77
- * Flush the data cache to memory 
78
- * 
79
- * Different systems have different cache line sizes
80
- * and in some cases i-cache and d-cache line sizes differ from
81
- * each other.
82
- */
83
- 	ld	r10,PPC64_CACHES@toc(r2)
84
-	lwz	r7,DCACHEL1BLOCKSIZE(r10)/* Get cache block size */
85
-	addi	r5,r7,-1
86
-	andc	r6,r3,r5		/* round low to line bdy */
87
-	subf	r8,r6,r4		/* compute length */
88
-	add	r8,r8,r5		/* ensure we get enough */
89
-	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of cache block size */
90
-	srd.	r8,r8,r9		/* compute line count */
91
-	beqlr				/* nothing to do? */
92
-	mtctr	r8
93
-1:	dcbst	0,r6
94
-	add	r6,r6,r7
95
-	bdnz	1b
96
-	sync
97
-
98
-/* Now invalidate the instruction cache */
99
-	
100
-	lwz	r7,ICACHEL1BLOCKSIZE(r10)	/* Get Icache block size */
101
-	addi	r5,r7,-1
102
-	andc	r6,r3,r5		/* round low to line bdy */
103
-	subf	r8,r6,r4		/* compute length */
104
-	add	r8,r8,r5
105
-	lwz	r9,ICACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of Icache block size */
106
-	srd.	r8,r8,r9		/* compute line count */
107
-	beqlr				/* nothing to do? */
108
-	mtctr	r8
109
-2:	icbi	0,r6
110
-	add	r6,r6,r7
111
-	bdnz	2b
112
-	isync
113
-	blr
114
-_ASM_NOKPROBE_SYMBOL(flush_icache_range)
115
-EXPORT_SYMBOL(flush_icache_range)
116
-
117
-/*
118
- * Like above, but only do the D-cache.
119
- *
120
- * flush_dcache_range(unsigned long start, unsigned long stop)
121
- *
122
- *    flush all bytes from start to stop-1 inclusive
123
- */
124
-_GLOBAL_TOC(flush_dcache_range)
125
-
126
-/*
127
- * Flush the data cache to memory 
128
- * 
129
- * Different systems have different cache line sizes
130
- */
131
- 	ld	r10,PPC64_CACHES@toc(r2)
132
-	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */
133
-	addi	r5,r7,-1
134
-	andc	r6,r3,r5		/* round low to line bdy */
135
-	subf	r8,r6,r4		/* compute length */
136
-	add	r8,r8,r5		/* ensure we get enough */
137
-	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of dcache block size */
138
-	srd.	r8,r8,r9		/* compute line count */
139
-	beqlr				/* nothing to do? */
140
-	mtctr	r8
141
-0:	dcbst	0,r6
142
-	add	r6,r6,r7
143
-	bdnz	0b
144
-	sync
145
-	blr
146
-EXPORT_SYMBOL(flush_dcache_range)
147
-
148
-_GLOBAL(flush_inval_dcache_range)
149
- 	ld	r10,PPC64_CACHES@toc(r2)
150
-	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */
151
-	addi	r5,r7,-1
152
-	andc	r6,r3,r5		/* round low to line bdy */
153
-	subf	r8,r6,r4		/* compute length */
154
-	add	r8,r8,r5		/* ensure we get enough */
155
-	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)/* Get log-2 of dcache block size */
156
-	srd.	r8,r8,r9		/* compute line count */
157
-	beqlr				/* nothing to do? */
158
-	sync
159
-	isync
160
-	mtctr	r8
161
-0:	dcbf	0,r6
162
-	add	r6,r6,r7
163
-	bdnz	0b
164
-	sync
165
-	isync
166
-	blr
167
-
168
-
169
-/*
170
- * Flush a particular page from the data cache to RAM.
171
- * Note: this is necessary because the instruction cache does *not*
172
- * snoop from the data cache.
173
- *
174
- *	void __flush_dcache_icache(void *page)
175
- */
176
-_GLOBAL(__flush_dcache_icache)
177
-/*
178
- * Flush the data cache to memory 
179
- * 
180
- * Different systems have different cache line sizes
181
- */
182
-
183
-BEGIN_FTR_SECTION
184
-	PURGE_PREFETCHED_INS
185
-	blr
186
-END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
187
-
188
-/* Flush the dcache */
189
- 	ld	r7,PPC64_CACHES@toc(r2)
190
-	clrrdi	r3,r3,PAGE_SHIFT           	    /* Page align */
191
-	lwz	r4,DCACHEL1BLOCKSPERPAGE(r7)	/* Get # dcache blocks per page */
192
-	lwz	r5,DCACHEL1BLOCKSIZE(r7)	/* Get dcache block size */
193
-	mr	r6,r3
194
-	mtctr	r4
195
-0:	dcbst	0,r6
196
-	add	r6,r6,r5
197
-	bdnz	0b
198
-	sync
199
-
200
-/* Now invalidate the icache */	
201
-
202
-	lwz	r4,ICACHEL1BLOCKSPERPAGE(r7)	/* Get # icache blocks per page */
203
-	lwz	r5,ICACHEL1BLOCKSIZE(r7)	/* Get icache block size */
204
-	mtctr	r4
205
-1:	icbi	0,r3
206
-	add	r3,r3,r5
207
-	bdnz	1b
208
-	isync
20950 	blr
21051 
21152 _GLOBAL(__bswapdi2)
....@@ -489,18 +330,13 @@
489330 	rlwimi	r9,r10,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r9) */
490331 
491332 /* Set up a temp identity mapping v:0 to p:0 and return to it. */
492
-#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
493
-#define M_IF_NEEDED	MAS2_M
494
-#else
495
-#define M_IF_NEEDED	0
496
-#endif
497333 	mtspr	SPRN_MAS0,r9
498334 
499335 	lis	r9,(MAS1_VALID|MAS1_IPROT)@h
500336 	ori	r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
501337 	mtspr	SPRN_MAS1,r9
502338 
503
-	LOAD_REG_IMMEDIATE(r9, 0x0 | M_IF_NEEDED)
339
+	LOAD_REG_IMMEDIATE(r9, 0x0 | MAS2_M_IF_NEEDED)
504340 	mtspr	SPRN_MAS2,r9
505341 
506342 	LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
....@@ -529,7 +365,6 @@
529365 
530366 	li	r4,KEXEC_STATE_REAL_MODE
531367 	stb	r4,PACAKEXECSTATE(r13)
532
-	SYNC
533368 
534369 	b	kexec_wait
535370 
....@@ -576,20 +411,6 @@
576411 
577412 	li	r0,0
578413 	std	r0,16(r1)
579
-
580
-BEGIN_FTR_SECTION
581
-	/*
582
-	 * This is the best time to turn AMR/IAMR off.
583
-	 * key 0 is used in radix for supervisor<->user
584
-	 * protection, but on hash key 0 is reserved
585
-	 * ideally we want to enter with a clean state.
586
-	 * NOTE, we rely on r0 being 0 from above.
587
-	 */
588
-	mtspr	SPRN_IAMR,r0
589
-BEGIN_FTR_SECTION_NESTED(42)
590
-	mtspr	SPRN_AMOR,r0
591
-END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
592
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
593414 
594415 	/* save regs for local vars on new stack.
595416 	 * yes, we won't go back, but ...