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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/arch/mips/pci/pci-ip27.c
....@@ -7,217 +7,12 @@
77  * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
88  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
99  */
10
-#include <linux/kernel.h>
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-#include <linux/export.h>
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-#include <linux/pci.h>
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-#include <linux/smp.h>
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-#include <linux/dma-direct.h>
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-#include <asm/sn/arch.h>
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+#include <asm/sn/addrs.h>
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+#include <asm/sn/types.h>
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+#include <asm/sn/klconfig.h>
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+#include <asm/sn/agent.h>
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+#include <asm/sn/ioc3.h>
1615 #include <asm/pci/bridge.h>
17
-#include <asm/paccess.h>
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-#include <asm/sn/intr.h>
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-#include <asm/sn/sn0/hub.h>
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-
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-/*
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- * Max #PCI busses we can handle; ie, max #PCI bridges.
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- */
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-#define MAX_PCI_BUSSES		40
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-
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-/*
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- * Max #PCI devices (like scsi controllers) we handle on a bus.
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- */
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-#define MAX_DEVICES_PER_PCIBUS	8
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-
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-/*
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- * XXX: No kmalloc available when we do our crosstalk scan,
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- *	we should try to move it later in the boot process.
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- */
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-static struct bridge_controller bridges[MAX_PCI_BUSSES];
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-
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-/*
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- * Translate from irq to software PCI bus number and PCI slot.
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- */
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-struct bridge_controller *irq_to_bridge[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
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-int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
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-
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-extern struct pci_ops bridge_pci_ops;
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-
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-int bridge_probe(nasid_t nasid, int widget_id, int masterwid)
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-{
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-	unsigned long offset = NODE_OFFSET(nasid);
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-	struct bridge_controller *bc;
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-	static int num_bridges = 0;
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-	bridge_t *bridge;
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-	int slot;
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-
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-	pci_set_flags(PCI_PROBE_ONLY);
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-
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-	printk("a bridge\n");
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-
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-	/* XXX: kludge alert.. */
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-	if (!num_bridges)
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-		ioport_resource.end = ~0UL;
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-
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-	bc = &bridges[num_bridges];
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-
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-	bc->pc.pci_ops		= &bridge_pci_ops;
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-	bc->pc.mem_resource	= &bc->mem;
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-	bc->pc.io_resource	= &bc->io;
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-
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-	bc->pc.index		= num_bridges;
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-
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-	bc->mem.name		= "Bridge PCI MEM";
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-	bc->pc.mem_offset	= offset;
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-	bc->mem.start		= 0;
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-	bc->mem.end		= ~0UL;
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-	bc->mem.flags		= IORESOURCE_MEM;
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-
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-	bc->io.name		= "Bridge IO MEM";
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-	bc->pc.io_offset	= offset;
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-	bc->io.start		= 0UL;
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-	bc->io.end		= ~0UL;
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-	bc->io.flags		= IORESOURCE_IO;
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-
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-	bc->irq_cpu = smp_processor_id();
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-	bc->widget_id = widget_id;
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-	bc->nasid = nasid;
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-
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-	bc->baddr = (u64)masterwid << 60 | PCI64_ATTR_BAR;
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-
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-	/*
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-	 * point to this bridge
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-	 */
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-	bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
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-
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-	/*
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-	 * Clear all pending interrupts.
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-	 */
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-	bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
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-
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-	/*
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-	 * Until otherwise set up, assume all interrupts are from slot 0
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-	 */
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-	bridge->b_int_device = 0x0;
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-
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-	/*
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-	 * swap pio's to pci mem and io space (big windows)
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-	 */
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-	bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
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-				 BRIDGE_CTRL_MEM_SWAP;
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-#ifdef CONFIG_PAGE_SIZE_4KB
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-	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
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-#else /* 16kB or larger */
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-	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
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-#endif
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-
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-	/*
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-	 * Hmm...  IRIX sets additional bits in the address which
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-	 * are documented as reserved in the bridge docs.
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-	 */
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-	bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
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-	bridge->b_wid_int_lower = 0x01800090;	/* PI_INT_PEND_MOD off*/
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-	bridge->b_dir_map = (masterwid << 20);	/* DMA */
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-	bridge->b_int_enable = 0;
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-
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-	for (slot = 0; slot < 8; slot ++) {
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-		bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
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-		bc->pci_int[slot] = -1;
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-	}
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-	bridge->b_wid_tflush;	  /* wait until Bridge PIO complete */
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-
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-	bc->base = bridge;
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-
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-	register_pci_controller(&bc->pc);
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-
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-	num_bridges++;
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-
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-	return 0;
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-}
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-
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-/*
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- * All observed requests have pin == 1. We could have a global here, that
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- * gets incremented and returned every time - unfortunately, pci_map_irq
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- * may be called on the same device over and over, and need to return the
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- * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
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- *
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- * A given PCI device, in general, should be able to intr any of the cpus
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- * on any one of the hubs connected to its xbow.
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- */
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-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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-{
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-	return 0;
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-}
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-
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-static inline struct pci_dev *bridge_root_dev(struct pci_dev *dev)
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-{
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-	while (dev->bus->parent) {
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-		/* Move up the chain of bridges. */
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-		dev = dev->bus->self;
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-	}
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-
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-	return dev;
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-}
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-
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-/* Do platform specific device initialization at pci_enable_device() time */
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-int pcibios_plat_dev_init(struct pci_dev *dev)
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-{
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-	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
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-	struct pci_dev *rdev = bridge_root_dev(dev);
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-	int slot = PCI_SLOT(rdev->devfn);
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-	int irq;
168
-
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-	irq = bc->pci_int[slot];
170
-	if (irq == -1) {
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-		irq = request_bridge_irq(bc);
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-		if (irq < 0)
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-			return irq;
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-
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-		bc->pci_int[slot] = irq;
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-	}
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-
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-	irq_to_bridge[irq] = bc;
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-	irq_to_slot[irq] = slot;
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-
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-	dev->irq = irq;
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-
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-	return 0;
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-}
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-
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-dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
187
-{
188
-	struct pci_dev *pdev = to_pci_dev(dev);
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-	struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
190
-
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-	return bc->baddr + paddr;
192
-}
193
-
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-phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
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-{
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-	return dma_addr & ~(0xffUL << 56);
197
-}
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-
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-/*
200
- * Device might live on a subordinate PCI bus.	XXX Walk up the chain of buses
201
- * to find the slot number in sense of the bridge device register.
202
- * XXX This also means multiple devices might rely on conflicting bridge
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- * settings.
204
- */
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-
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-static inline void pci_disable_swapping(struct pci_dev *dev)
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-{
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-	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
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-	bridge_t *bridge = bc->base;
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-	int slot = PCI_SLOT(dev->devfn);
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-
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-	/* Turn off byte swapping */
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-	bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
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-	bridge->b_widget.w_tflush;	/* Flush */
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-}
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-
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-static void pci_fixup_ioc3(struct pci_dev *d)
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-{
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-	pci_disable_swapping(d);
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-}
22116 
22217 #ifdef CONFIG_NUMA
22318 int pcibus_to_node(struct pci_bus *bus)
....@@ -229,5 +24,19 @@
22924 EXPORT_SYMBOL(pcibus_to_node);
23025 #endif /* CONFIG_NUMA */
23126 
232
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
233
-	pci_fixup_ioc3);
27
+static void ip29_fixup_phy(struct pci_dev *dev)
28
+{
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+	int nasid = pcibus_to_node(dev->bus);
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+	u32 sid;
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+
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+	if (nasid != 1)
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+		return; /* only needed on second module */
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+
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+	/* enable ethernet PHY on IP29 systemboard */
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+	pci_read_config_dword(dev, PCI_SUBSYSTEM_VENDOR_ID, &sid);
37
+	if (sid == (PCI_VENDOR_ID_SGI | (IOC3_SUBSYS_IP29_SYSBOARD) << 16))
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+		REMOTE_HUB_S(nasid, MD_LED0, 0x09);
39
+}
40
+
41
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
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+			ip29_fixup_phy);