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2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc 
 kernel/arch/arm/mm/Kconfig
....@@ -106,7 +106,7 @@
106106 	help
107107 	  The ARM922T is a version of the ARM920T, but with smaller
108108 	  instruction and data caches. It is used in Altera's
109
-	  Excalibur XA device family and Micrel's KS8695 Centaur.
109
+	  Excalibur XA device family and the ARM Integrator.
110110 
111111 	  Say Y if you want support for the ARM922T processor.
112112 	  Otherwise, say N.
....@@ -710,7 +710,7 @@
710710 	  assistance.
711711 
712712 	  A compliant bootloader is required in order to make maximum
713
-	  use of this feature.  Refer to Documentation/arm/Booting for
713
+	  use of this feature.  Refer to Documentation/arm/booting.rst for
714714 	  details.
715715 
716716 config SWP_EMULATE
....@@ -743,6 +743,7 @@
743743 config CPU_BIG_ENDIAN
744744 	bool "Build big-endian kernel"
745745 	depends on ARCH_SUPPORTS_BIG_ENDIAN
746
+	depends on !LD_IS_LLD
746747 	help
747748 	  Say Y if you plan on running a kernel in big-endian mode.
748749 	  Note that your board must be properly built and your board
....@@ -780,6 +781,14 @@
780781 	help
781782 	  Say Y here to disable the processor instruction cache. Unless
782783 	  you have a reason not to or are unsure, say N.
784
+
785
+config CPU_ICACHE_MISMATCH_WORKAROUND
786
+	bool "Workaround for I-Cache line size mismatch between CPU cores"
787
+	depends on SMP && CPU_V7
788
+	help
789
+	  Some big.LITTLE systems have I-Cache line size mismatch between
790
+	  LITTLE and big cores.  Say Y here to enable a workaround for
791
+	  proper I-Cache support on such systems.  If unsure, say N.
783792 
784793 config CPU_DCACHE_DISABLE
785794 	bool "Disable D-Cache (C-bit)"
....@@ -824,6 +833,7 @@
824833 
825834 config CPU_SPECTRE
826835 	bool
836
+	select GENERIC_CPU_VULNERABILITIES
827837 
828838 config HARDEN_BRANCH_PREDICTOR
829839 	bool "Harden the branch predictor against aliasing attacks" if EXPERT
....@@ -843,6 +853,16 @@
843853 	   the system firmware.
844854 
845855 	   If unsure, say Y.
856
+
857
+config HARDEN_BRANCH_HISTORY
858
+	bool "Harden Spectre style attacks against branch history" if EXPERT
859
+	depends on CPU_SPECTRE
860
+	default y
861
+	help
862
+	  Speculation attacks against some high-performance processors can
863
+	  make use of branch history to influence future speculation. When
864
+	  taking an exception, a sequence of branches overwrites the branch
865
+	  history, or branch history is invalidated.
846866 
847867 config TLS_REG_EMUL
848868 	bool
....@@ -868,7 +888,7 @@
868888 	  the CPU type fitted to the system.  This permits binaries to be
869889 	  run on ARMv4 through to ARMv7 without modification.
870890 
871
-	  See Documentation/arm/kernel_user_helpers.txt for details.
891
+	  See Documentation/arm/kernel_user_helpers.rst for details.
872892 
873893 	  However, the fixed address nature of these helpers can be used
874894 	  by ROP (return orientated programming) authors when creating
....@@ -888,7 +908,10 @@
888908 	bool "Enable VDSO for acceleration of some system calls"
889909 	depends on AEABI && MMU && CPU_V7
890910 	default y if ARM_ARCH_TIMER
911
+	select HAVE_GENERIC_VDSO
891912 	select GENERIC_TIME_VSYSCALL
913
+	select GENERIC_VDSO_32
914
+	select GENERIC_GETTIMEOFDAY
892915 	help
893916 	  Place in the process address space an ELF shared object
894917 	  providing fast implementations of gettimeofday and
....@@ -1033,7 +1056,7 @@
10331056 
10341057 config CACHE_TAUROS2
10351058 	bool "Enable the Tauros2 L2 cache controller"
1036
-	depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
1059
+	depends on (CPU_MOHAWK || CPU_PJ4)
10371060 	default y
10381061 	select OUTER_CACHE
10391062 	help