write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/arm/mach-tegra/reset.h
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@@ -1,19 +1,10 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * arch/arm/mach-tegra/reset.h
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  *
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  * CPU reset dispatcher.
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  *
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  * Copyright (c) 2011, NVIDIA Corporation.
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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  */
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 #ifndef __MACH_TEGRA_RESET_H
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@@ -25,7 +16,10 @@
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 #define TEGRA_RESET_STARTUP_SECONDARY	3
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 #define TEGRA_RESET_STARTUP_LP2		4
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 #define TEGRA_RESET_STARTUP_LP1		5
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-#define TEGRA_RESET_DATA_SIZE		6
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+#define TEGRA_RESET_TF_PRESENT		6
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+#define TEGRA_RESET_DATA_SIZE		7
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+
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+#define RESET_DATA(x)	((TEGRA_RESET_##x)*4)
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 #ifndef __ASSEMBLY__
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@@ -47,9 +41,6 @@
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 	(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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 	((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
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 	 (u32)__tegra_cpu_reset_handler_start)))
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-#define tegra20_cpu1_resettable_status \
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-	(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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-	 (u32)__tegra20_cpu1_resettable_status_offset))
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 #endif
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 #define tegra_cpu_reset_handler_offset \