write in 30M

hc

2024-02-20 ea08eeccae9297f7aabd2ef7f0c2517ac4549acc

 kernel/arch/arm/mach-mmp/time.c
..
..
@@ -43,18 +43,21 @@
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 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
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 /*
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- * FIXME: the timer needs some delay to stablize the counter capture
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+ * Read the timer through the CVWR register. Delay is required after requesting
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+ * a read. The CR register cannot be directly read due to metastability issues
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+ * documented in the PXA168 software manual.
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  */
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 static inline uint32_t timer_read(void)
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 {
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-	int delay = 100;
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+	uint32_t val;
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+	int delay = 3;
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 	__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
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 	while (delay--)
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-		cpu_relax();
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+		val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
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-	return __raw_readl(mmp_timer_base + TMR_CVWR(1));
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+	return val;
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 }
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 static u64 notrace mmp_read_sched_clock(void)