debug lk

hc

2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077

 kernel/tools/perf/pmu-events/arch/x86/haswellx/cache.json
..
..
@@ -64,18 +64,18 @@
64
64
     },
65
65
     {
66
66
         "EventCode": "0x24",
67
-        "UMask": "0x41",
67
+        "UMask": "0xc1",
68
68
         "BriefDescription": "Demand Data Read requests that hit L2 cache",
69
69
         "Counter": "0,1,2,3",
70
70
         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
71
71
         "Errata": "HSD78",
72
-        "PublicDescription": "Demand data read requests that hit L2 cache.",
72
+        "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
73
73
         "SampleAfterValue": "200003",
74
74
         "CounterHTOff": "0,1,2,3,4,5,6,7"
75
75
     },
76
76
     {
77
77
         "EventCode": "0x24",
78
-        "UMask": "0x42",
78
+        "UMask": "0xc2",
79
79
         "BriefDescription": "RFO requests that hit L2 cache",
80
80
         "Counter": "0,1,2,3",
81
81
         "EventName": "L2_RQSTS.RFO_HIT",
..
..
@@ -85,7 +85,7 @@
85
85
     },
86
86
     {
87
87
         "EventCode": "0x24",
88
-        "UMask": "0x44",
88
+        "UMask": "0xc4",
89
89
         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
90
90
         "Counter": "0,1,2,3",
91
91
         "EventName": "L2_RQSTS.CODE_RD_HIT",
..
..
@@ -95,7 +95,7 @@
95
95
     },
96
96
     {
97
97
         "EventCode": "0x24",
98
-        "UMask": "0x50",
98
+        "UMask": "0xd0",
99
99
         "BriefDescription": "L2 prefetch requests that hit L2 cache",
100
100
         "Counter": "0,1,2,3",
101
101
         "EventName": "L2_RQSTS.L2_PF_HIT",
..
..
@@ -416,7 +416,7 @@
416
416
     {
417
417
         "EventCode": "0xD0",
418
418
         "UMask": "0x11",
419
-        "BriefDescription": "Retired load uops that miss the STLB. (precise Event)",
419
+        "BriefDescription": "Retired load uops that miss the STLB.",
420
420
         "Data_LA": "1",
421
421
         "PEBS": "1",
422
422
         "Counter": "0,1,2,3",
..
..
@@ -428,7 +428,7 @@
428
428
     {
429
429
         "EventCode": "0xD0",
430
430
         "UMask": "0x12",
431
-        "BriefDescription": "Retired store uops that miss the STLB. (precise Event)",
431
+        "BriefDescription": "Retired store uops that miss the STLB.",
432
432
         "Data_LA": "1",
433
433
         "PEBS": "1",
434
434
         "Counter": "0,1,2,3",
..
..
@@ -441,7 +441,7 @@
441
441
     {
442
442
         "EventCode": "0xD0",
443
443
         "UMask": "0x21",
444
-        "BriefDescription": "Retired load uops with locked access. (precise Event)",
444
+        "BriefDescription": "Retired load uops with locked access.",
445
445
         "Data_LA": "1",
446
446
         "PEBS": "1",
447
447
         "Counter": "0,1,2,3",
..
..
@@ -453,34 +453,32 @@
453
453
     {
454
454
         "EventCode": "0xD0",
455
455
         "UMask": "0x41",
456
-        "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)",
456
+        "BriefDescription": "Retired load uops that split across a cacheline boundary.",
457
457
         "Data_LA": "1",
458
458
         "PEBS": "1",
459
459
         "Counter": "0,1,2,3",
460
460
         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
461
461
         "Errata": "HSD29, HSM30",
462
-        "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
463
462
         "SampleAfterValue": "100003",
464
463
         "CounterHTOff": "0,1,2,3"
465
464
     },
466
465
     {
467
466
         "EventCode": "0xD0",
468
467
         "UMask": "0x42",
469
-        "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)",
468
+        "BriefDescription": "Retired store uops that split across a cacheline boundary.",
470
469
         "Data_LA": "1",
471
470
         "PEBS": "1",
472
471
         "Counter": "0,1,2,3",
473
472
         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
474
473
         "Errata": "HSD29, HSM30",
475
474
         "L1_Hit_Indication": "1",
476
-        "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
477
475
         "SampleAfterValue": "100003",
478
476
         "CounterHTOff": "0,1,2,3"
479
477
     },
480
478
     {
481
479
         "EventCode": "0xD0",
482
480
         "UMask": "0x81",
483
-        "BriefDescription": "All retired load uops. (precise Event)",
481
+        "BriefDescription": "All retired load uops.",
484
482
         "Data_LA": "1",
485
483
         "PEBS": "1",
486
484
         "Counter": "0,1,2,3",
..
..
@@ -492,14 +490,13 @@
492
490
     {
493
491
         "EventCode": "0xD0",
494
492
         "UMask": "0x82",
495
-        "BriefDescription": "All retired store uops. (precise Event)",
493
+        "BriefDescription": "All retired store uops.",
496
494
         "Data_LA": "1",
497
495
         "PEBS": "1",
498
496
         "Counter": "0,1,2,3",
499
497
         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
500
498
         "Errata": "HSD29, HSM30",
501
499
         "L1_Hit_Indication": "1",
502
-        "PublicDescription": "This event counts all store uops retired. This is a precise event.",
503
500
         "SampleAfterValue": "2000003",
504
501
         "CounterHTOff": "0,1,2,3"
505
502
     },
..
..
@@ -530,13 +527,13 @@
530
527
     {
531
528
         "EventCode": "0xD1",
532
529
         "UMask": "0x4",
533
-        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
530
+        "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
534
531
         "Data_LA": "1",
535
532
         "PEBS": "1",
536
533
         "Counter": "0,1,2,3",
537
534
         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
538
535
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
539
-        "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.",
536
+        "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
540
537
         "SampleAfterValue": "50021",
541
538
         "CounterHTOff": "0,1,2,3"
542
539
     },
..
..
@@ -549,19 +546,20 @@
549
546
         "Counter": "0,1,2,3",
550
547
         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
551
548
         "Errata": "HSM30",
552
-        "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.",
549
+        "PublicDescription": "Retired load uops missed L1 cache as data sources.",
553
550
         "SampleAfterValue": "100003",
554
551
         "CounterHTOff": "0,1,2,3"
555
552
     },
556
553
     {
557
554
         "EventCode": "0xD1",
558
555
         "UMask": "0x10",
559
-        "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
556
+        "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
560
557
         "Data_LA": "1",
561
558
         "PEBS": "1",
562
559
         "Counter": "0,1,2,3",
563
560
         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
564
561
         "Errata": "HSD29, HSM30",
562
+        "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
565
563
         "SampleAfterValue": "50021",
566
564
         "CounterHTOff": "0,1,2,3"
567
565
     },
..
..
@@ -574,6 +572,7 @@
574
572
         "Counter": "0,1,2,3",
575
573
         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
576
574
         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
575
+        "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
577
576
         "SampleAfterValue": "100003",
578
577
         "CounterHTOff": "0,1,2,3"
579
578
     },
..
..
@@ -604,26 +603,24 @@
604
603
     {
605
604
         "EventCode": "0xD2",
606
605
         "UMask": "0x2",
607
-        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ",
606
+        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
608
607
         "Data_LA": "1",
609
608
         "PEBS": "1",
610
609
         "Counter": "0,1,2,3",
611
610
         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
612
611
         "Errata": "HSD29, HSD25, HSM26, HSM30",
613
-        "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
614
612
         "SampleAfterValue": "20011",
615
613
         "CounterHTOff": "0,1,2,3"
616
614
     },
617
615
     {
618
616
         "EventCode": "0xD2",
619
617
         "UMask": "0x4",
620
-        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ",
618
+        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
621
619
         "Data_LA": "1",
622
620
         "PEBS": "1",
623
621
         "Counter": "0,1,2,3",
624
622
         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
625
623
         "Errata": "HSD29, HSD25, HSM26, HSM30",
626
-        "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
627
624
         "SampleAfterValue": "20011",
628
625
         "CounterHTOff": "0,1,2,3"
629
626
     },
..
..
@@ -642,19 +639,20 @@
642
639
     {
643
640
         "EventCode": "0xD3",
644
641
         "UMask": "0x1",
642
+        "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
645
643
         "Data_LA": "1",
646
644
         "PEBS": "1",
647
645
         "Counter": "0,1,2,3",
648
646
         "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
649
647
         "Errata": "HSD74, HSD29, HSD25, HSM30",
650
-        "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
648
+        "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
651
649
         "SampleAfterValue": "100003",
652
650
         "CounterHTOff": "0,1,2,3"
653
651
     },
654
652
     {
655
653
         "EventCode": "0xD3",
656
654
         "UMask": "0x4",
657
-        "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
655
+        "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
658
656
         "Data_LA": "1",
659
657
         "PEBS": "1",
660
658
         "Counter": "0,1,2,3",
..
..
@@ -666,7 +664,7 @@
666
664
     {
667
665
         "EventCode": "0xD3",
668
666
         "UMask": "0x10",
669
-        "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
667
+        "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
670
668
         "Data_LA": "1",
671
669
         "PEBS": "1",
672
670
         "Counter": "0,1,2,3",
..
..
@@ -678,7 +676,7 @@
678
676
     {
679
677
         "EventCode": "0xD3",
680
678
         "UMask": "0x20",
681
-        "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
679
+        "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
682
680
         "Data_LA": "1",
683
681
         "PEBS": "1",
684
682
         "Counter": "0,1,2,3",
..
..
@@ -833,7 +831,6 @@
833
831
         "BriefDescription": "Split locks in SQ",
834
832
         "Counter": "0,1,2,3",
835
833
         "EventName": "SQ_MISC.SPLIT_LOCK",
836
-        "PublicDescription": "",
837
834
         "SampleAfterValue": "100003",
838
835
         "CounterHTOff": "0,1,2,3,4,5,6,7"
839
836
     },
..
..
@@ -841,12 +838,12 @@
841
838
         "Offcore": "1",
842
839
         "EventCode": "0xB7, 0xBB",
843
840
         "UMask": "0x1",
844
-        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
845
-        "MSRValue": "0x04003c0001",
841
+        "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
842
+        "MSRValue": "0x04003C0001",
846
843
         "Counter": "0,1,2,3",
847
844
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
848
845
         "MSRIndex": "0x1a6,0x1a7",
849
-        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
846
+        "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
850
847
         "SampleAfterValue": "100003",
851
848
         "CounterHTOff": "0,1,2,3"
852
849
     },
..
..
@@ -854,12 +851,12 @@
854
851
         "Offcore": "1",
855
852
         "EventCode": "0xB7, 0xBB",
856
853
         "UMask": "0x1",
857
-        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
858
-        "MSRValue": "0x10003c0001",
854
+        "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
855
+        "MSRValue": "0x10003C0001",
859
856
         "Counter": "0,1,2,3",
860
857
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
861
858
         "MSRIndex": "0x1a6,0x1a7",
862
-        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
859
+        "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
863
860
         "SampleAfterValue": "100003",
864
861
         "CounterHTOff": "0,1,2,3"
865
862
     },
..
..
@@ -867,12 +864,12 @@
867
864
         "Offcore": "1",
868
865
         "EventCode": "0xB7, 0xBB",
869
866
         "UMask": "0x1",
870
-        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
871
-        "MSRValue": "0x04003c0002",
867
+        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
868
+        "MSRValue": "0x04003C0002",
872
869
         "Counter": "0,1,2,3",
873
870
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
874
871
         "MSRIndex": "0x1a6,0x1a7",
875
-        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
872
+        "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
876
873
         "SampleAfterValue": "100003",
877
874
         "CounterHTOff": "0,1,2,3"
878
875
     },
..
..
@@ -880,12 +877,12 @@
880
877
         "Offcore": "1",
881
878
         "EventCode": "0xB7, 0xBB",
882
879
         "UMask": "0x1",
883
-        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
884
-        "MSRValue": "0x10003c0002",
880
+        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
881
+        "MSRValue": "0x10003C0002",
885
882
         "Counter": "0,1,2,3",
886
883
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
887
884
         "MSRIndex": "0x1a6,0x1a7",
888
-        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
885
+        "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
889
886
         "SampleAfterValue": "100003",
890
887
         "CounterHTOff": "0,1,2,3"
891
888
     },
..
..
@@ -893,12 +890,12 @@
893
890
         "Offcore": "1",
894
891
         "EventCode": "0xB7, 0xBB",
895
892
         "UMask": "0x1",
896
-        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
897
-        "MSRValue": "0x04003c0004",
893
+        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
894
+        "MSRValue": "0x04003C0004",
898
895
         "Counter": "0,1,2,3",
899
896
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
900
897
         "MSRIndex": "0x1a6,0x1a7",
901
-        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
898
+        "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
902
899
         "SampleAfterValue": "100003",
903
900
         "CounterHTOff": "0,1,2,3"
904
901
     },
..
..
@@ -906,12 +903,12 @@
906
903
         "Offcore": "1",
907
904
         "EventCode": "0xB7, 0xBB",
908
905
         "UMask": "0x1",
909
-        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
910
-        "MSRValue": "0x10003c0004",
906
+        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
907
+        "MSRValue": "0x10003C0004",
911
908
         "Counter": "0,1,2,3",
912
909
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
913
910
         "MSRIndex": "0x1a6,0x1a7",
914
-        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
911
+        "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
915
912
         "SampleAfterValue": "100003",
916
913
         "CounterHTOff": "0,1,2,3"
917
914
     },
..
..
@@ -919,12 +916,12 @@
919
916
         "Offcore": "1",
920
917
         "EventCode": "0xB7, 0xBB",
921
918
         "UMask": "0x1",
922
-        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",
923
-        "MSRValue": "0x3f803c0010",
919
+        "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
920
+        "MSRValue": "0x3F803C0010",
924
921
         "Counter": "0,1,2,3",
925
922
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
926
923
         "MSRIndex": "0x1a6,0x1a7",
927
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
924
+        "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
928
925
         "SampleAfterValue": "100003",
929
926
         "CounterHTOff": "0,1,2,3"
930
927
     },
..
..
@@ -932,12 +929,12 @@
932
929
         "Offcore": "1",
933
930
         "EventCode": "0xB7, 0xBB",
934
931
         "UMask": "0x1",
935
-        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",
936
-        "MSRValue": "0x3f803c0020",
932
+        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
933
+        "MSRValue": "0x3F803C0020",
937
934
         "Counter": "0,1,2,3",
938
935
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
939
936
         "MSRIndex": "0x1a6,0x1a7",
940
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
937
+        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
941
938
         "SampleAfterValue": "100003",
942
939
         "CounterHTOff": "0,1,2,3"
943
940
     },
..
..
@@ -945,12 +942,12 @@
945
942
         "Offcore": "1",
946
943
         "EventCode": "0xB7, 0xBB",
947
944
         "UMask": "0x1",
948
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",
949
-        "MSRValue": "0x3f803c0040",
945
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
946
+        "MSRValue": "0x3F803C0040",
950
947
         "Counter": "0,1,2,3",
951
948
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
952
949
         "MSRIndex": "0x1a6,0x1a7",
953
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
950
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
954
951
         "SampleAfterValue": "100003",
955
952
         "CounterHTOff": "0,1,2,3"
956
953
     },
..
..
@@ -958,12 +955,12 @@
958
955
         "Offcore": "1",
959
956
         "EventCode": "0xB7, 0xBB",
960
957
         "UMask": "0x1",
961
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",
962
-        "MSRValue": "0x3f803c0080",
958
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
959
+        "MSRValue": "0x3F803C0080",
963
960
         "Counter": "0,1,2,3",
964
961
         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
965
962
         "MSRIndex": "0x1a6,0x1a7",
966
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
963
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
967
964
         "SampleAfterValue": "100003",
968
965
         "CounterHTOff": "0,1,2,3"
969
966
     },
..
..
@@ -971,12 +968,12 @@
971
968
         "Offcore": "1",
972
969
         "EventCode": "0xB7, 0xBB",
973
970
         "UMask": "0x1",
974
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3",
975
-        "MSRValue": "0x3f803c0100",
971
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
972
+        "MSRValue": "0x3F803C0100",
976
973
         "Counter": "0,1,2,3",
977
974
         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
978
975
         "MSRIndex": "0x1a6,0x1a7",
979
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
976
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
980
977
         "SampleAfterValue": "100003",
981
978
         "CounterHTOff": "0,1,2,3"
982
979
     },
..
..
@@ -984,12 +981,12 @@
984
981
         "Offcore": "1",
985
982
         "EventCode": "0xB7, 0xBB",
986
983
         "UMask": "0x1",
987
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",
988
-        "MSRValue": "0x3f803c0200",
984
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
985
+        "MSRValue": "0x3F803C0200",
989
986
         "Counter": "0,1,2,3",
990
987
         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
991
988
         "MSRIndex": "0x1a6,0x1a7",
992
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
989
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
993
990
         "SampleAfterValue": "100003",
994
991
         "CounterHTOff": "0,1,2,3"
995
992
     },
..
..
@@ -997,12 +994,12 @@
997
994
         "Offcore": "1",
998
995
         "EventCode": "0xB7, 0xBB",
999
996
         "UMask": "0x1",
1000
-        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1001
-        "MSRValue": "0x04003c0091",
997
+        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
998
+        "MSRValue": "0x04003C0091",
1002
999
         "Counter": "0,1,2,3",
1003
1000
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1004
1001
         "MSRIndex": "0x1a6,0x1a7",
1005
-        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1002
+        "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1006
1003
         "SampleAfterValue": "100003",
1007
1004
         "CounterHTOff": "0,1,2,3"
1008
1005
     },
..
..
@@ -1010,12 +1007,12 @@
1010
1007
         "Offcore": "1",
1011
1008
         "EventCode": "0xB7, 0xBB",
1012
1009
         "UMask": "0x1",
1013
-        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1014
-        "MSRValue": "0x10003c0091",
1010
+        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1011
+        "MSRValue": "0x10003C0091",
1015
1012
         "Counter": "0,1,2,3",
1016
1013
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1017
1014
         "MSRIndex": "0x1a6,0x1a7",
1018
-        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1015
+        "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1019
1016
         "SampleAfterValue": "100003",
1020
1017
         "CounterHTOff": "0,1,2,3"
1021
1018
     },
..
..
@@ -1023,12 +1020,12 @@
1023
1020
         "Offcore": "1",
1024
1021
         "EventCode": "0xB7, 0xBB",
1025
1022
         "UMask": "0x1",
1026
-        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1027
-        "MSRValue": "0x04003c0122",
1023
+        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1024
+        "MSRValue": "0x04003C0122",
1028
1025
         "Counter": "0,1,2,3",
1029
1026
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1030
1027
         "MSRIndex": "0x1a6,0x1a7",
1031
-        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1028
+        "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1032
1029
         "SampleAfterValue": "100003",
1033
1030
         "CounterHTOff": "0,1,2,3"
1034
1031
     },
..
..
@@ -1036,12 +1033,12 @@
1036
1033
         "Offcore": "1",
1037
1034
         "EventCode": "0xB7, 0xBB",
1038
1035
         "UMask": "0x1",
1039
-        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1040
-        "MSRValue": "0x10003c0122",
1036
+        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1037
+        "MSRValue": "0x10003C0122",
1041
1038
         "Counter": "0,1,2,3",
1042
1039
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
1043
1040
         "MSRIndex": "0x1a6,0x1a7",
1044
-        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1041
+        "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1045
1042
         "SampleAfterValue": "100003",
1046
1043
         "CounterHTOff": "0,1,2,3"
1047
1044
     },
..
..
@@ -1049,12 +1046,12 @@
1049
1046
         "Offcore": "1",
1050
1047
         "EventCode": "0xB7, 0xBB",
1051
1048
         "UMask": "0x1",
1052
-        "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1053
-        "MSRValue": "0x04003c0244",
1049
+        "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1050
+        "MSRValue": "0x04003C0244",
1054
1051
         "Counter": "0,1,2,3",
1055
1052
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1056
1053
         "MSRIndex": "0x1a6,0x1a7",
1057
-        "PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1054
+        "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1058
1055
         "SampleAfterValue": "100003",
1059
1056
         "CounterHTOff": "0,1,2,3"
1060
1057
     },
..
..
@@ -1062,12 +1059,12 @@
1062
1059
         "Offcore": "1",
1063
1060
         "EventCode": "0xB7, 0xBB",
1064
1061
         "UMask": "0x1",
1065
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1066
-        "MSRValue": "0x04003c07f7",
1062
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1063
+        "MSRValue": "0x04003C07F7",
1067
1064
         "Counter": "0,1,2,3",
1068
1065
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1069
1066
         "MSRIndex": "0x1a6,0x1a7",
1070
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1067
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1071
1068
         "SampleAfterValue": "100003",
1072
1069
         "CounterHTOff": "0,1,2,3"
1073
1070
     },
..
..
@@ -1075,12 +1072,12 @@
1075
1072
         "Offcore": "1",
1076
1073
         "EventCode": "0xB7, 0xBB",
1077
1074
         "UMask": "0x1",
1078
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1079
-        "MSRValue": "0x10003c07f7",
1075
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1076
+        "MSRValue": "0x10003C07F7",
1080
1077
         "Counter": "0,1,2,3",
1081
1078
         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
1082
1079
         "MSRIndex": "0x1a6,0x1a7",
1083
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1080
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1084
1081
         "SampleAfterValue": "100003",
1085
1082
         "CounterHTOff": "0,1,2,3"
1086
1083
     },
..
..
@@ -1088,12 +1085,12 @@
1088
1085
         "Offcore": "1",
1089
1086
         "EventCode": "0xB7, 0xBB",
1090
1087
         "UMask": "0x1",
1091
-        "BriefDescription": "Counts all requests that hit in the L3",
1092
-        "MSRValue": "0x3f803c8fff",
1088
+        "BriefDescription": "Counts all requests hit in the L3",
1089
+        "MSRValue": "0x3F803C8FFF",
1093
1090
         "Counter": "0,1,2,3",
1094
1091
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
1095
1092
         "MSRIndex": "0x1a6,0x1a7",
1096
-        "PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1093
+        "PublicDescription": "Counts all requests hit in the L3",
1097
1094
         "SampleAfterValue": "100003",
1098
1095
         "CounterHTOff": "0,1,2,3"
1099
1096
     }