forked from ~ljy/RK356X_SDK_RELEASE
kernel/tools/perf/pmu-events/arch/powerpc/power8/translation.json
.. .. @@ -1,176 +1,176 @@ 1 1 [ 2 2 3 3 "EventCode": "0x4c054", 4 4 "EventName": "PM_DERAT_MISS_16G", 5 5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", 6 6 "PublicDescription": "" 7 7 }, 8 8 9 9 "EventCode": "0x3c054", 10 10 "EventName": "PM_DERAT_MISS_16M", 11 11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M", 12 12 "PublicDescription": "" 13 13 }, 14 14 15 15 "EventCode": "0x1c056", 16 16 "EventName": "PM_DERAT_MISS_4K", 17 17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K", 18 18 "PublicDescription": "" 19 19 }, 20 20 21 21 "EventCode": "0x2c054", 22 22 "EventName": "PM_DERAT_MISS_64K", 23 23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K", 24 24 "PublicDescription": "" 25 25 }, 26 26 27 27 "EventCode": "0x4e048", 28 28 "EventName": "PM_DPTEG_FROM_DL2L3_MOD", 29 29 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", 30 30 "PublicDescription": "" 31 31 }, 32 32 33 33 "EventCode": "0x3e048", 34 34 "EventName": "PM_DPTEG_FROM_DL2L3_SHR", 35 35 "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", 36 36 "PublicDescription": "" 37 37 }, 38 38 39 39 "EventCode": "0x1e042", 40 40 "EventName": "PM_DPTEG_FROM_L2", 41 41 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request", 42 42 "PublicDescription": "" 43 43 }, 44 44 45 45 "EventCode": "0x1e04e", 46 46 "EventName": "PM_DPTEG_FROM_L2MISS", 47 47 48 48 "PublicDescription": "" 49 49 }, 50 50 51 51 "EventCode": "0x2e040", 52 52 "EventName": "PM_DPTEG_FROM_L2_MEPF", 53 53 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request", 54 54 "PublicDescription": "" 55 55 }, 56 56 57 57 "EventCode": "0x1e040", 58 58 "EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT", 59 59 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request", 60 60 "PublicDescription": "" 61 61 }, 62 62 63 63 "EventCode": "0x4e042", 64 64 "EventName": "PM_DPTEG_FROM_L3", 65 65 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request", 66 66 "PublicDescription": "" 67 67 }, 68 68 69 69 "EventCode": "0x3e042", 70 70 "EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT", 71 71 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request", 72 72 "PublicDescription": "" 73 73 }, 74 74 75 75 "EventCode": "0x2e042", 76 76 "EventName": "PM_DPTEG_FROM_L3_MEPF", 77 77 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request", 78 78 "PublicDescription": "" 79 79 }, 80 80 81 81 "EventCode": "0x1e044", 82 82 "EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT", 83 83 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request", 84 84 "PublicDescription": "" 85 85 }, 86 86 87 87 "EventCode": "0x1e04c", 88 88 "EventName": "PM_DPTEG_FROM_LL4", 89 89 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request", 90 90 "PublicDescription": "" 91 91 }, 92 92 93 93 "EventCode": "0x2e048", 94 94 "EventName": "PM_DPTEG_FROM_LMEM", 95 95 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request", 96 96 "PublicDescription": "" 97 97 }, 98 98 99 99 "EventCode": "0x2e04c", 100 100 "EventName": "PM_DPTEG_FROM_MEMORY", 101 101 "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request", 102 102 "PublicDescription": "" 103 103 }, 104 104 105 105 "EventCode": "0x4e04a", 106 106 "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE", 107 107 "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request", 108 108 "PublicDescription": "" 109 109 }, 110 110 111 111 "EventCode": "0x1e048", 112 112 "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE", 113 113 "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request", 114 114 "PublicDescription": "" 115 115 }, 116 116 117 117 "EventCode": "0x2e046", 118 118 "EventName": "PM_DPTEG_FROM_RL2L3_MOD", 119 119 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", 120 120 "PublicDescription": "" 121 121 }, 122 122 123 123 "EventCode": "0x1e04a", 124 124 "EventName": "PM_DPTEG_FROM_RL2L3_SHR", 125 125 "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", 126 126 "PublicDescription": "" 127 127 }, 128 128 129 129 "EventCode": "0x2e04a", 130 130 "EventName": "PM_DPTEG_FROM_RL4", 131 131 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request", 132 132 "PublicDescription": "" 133 133 }, 134 134 135 135 "EventCode": "0x300fc", 136 136 "EventName": "PM_DTLB_MISS", 137 137 "BriefDescription": "Data PTEG reload", 138 138 "PublicDescription": "Data PTEG Reloaded (DTLB Miss)" 139 139 }, 140 140 141 141 "EventCode": "0x1c058", 142 142 "EventName": "PM_DTLB_MISS_16G", 143 143 "BriefDescription": "Data TLB Miss page size 16G", 144 144 "PublicDescription": "" 145 145 }, 146 146 147 147 "EventCode": "0x4c056", 148 148 "EventName": "PM_DTLB_MISS_16M", 149 149 "BriefDescription": "Data TLB Miss page size 16M", 150 150 "PublicDescription": "" 151 151 }, 152 152 153 153 "EventCode": "0x2c056", 154 154 "EventName": "PM_DTLB_MISS_4K", 155 155 "BriefDescription": "Data TLB Miss page size 4k", 156 156 "PublicDescription": "" 157 157 }, 158 158 159 159 "EventCode": "0x3c056", 160 160 "EventName": "PM_DTLB_MISS_64K", 161 161 "BriefDescription": "Data TLB Miss page size 64K", 162 162 "PublicDescription": "" 163 163 }, 164 164 165 165 "EventCode": "0x200f6", 166 166 "EventName": "PM_LSU_DERAT_MISS", 167 167 "BriefDescription": "DERAT Reloaded due to a DERAT miss", 168 168 "PublicDescription": "DERAT Reloaded (Miss)" 169 169 }, 170 170 171 171 "EventCode": "0x20066", 172 172 "EventName": "PM_TLB_MISS", 173 173 "BriefDescription": "TLB Miss (I + D)", 174 174 "PublicDescription": "" 175 175 176 176 ]
