~hc/RK356X_SDK_RELEASE.git

..	..	@@ -19,6 +19,7 @@
19	19	#include <linux/clk.h>
20	20	#include <linux/clk-provider.h>
21	21	#include <linux/clk/rockchip.h>
	22	+#include <linux/pinctrl/consumer.h>
22	23	#include <linux/pm_runtime.h>
23	24	#include <linux/regmap.h>
24	25	#include <linux/reset.h>
..	..	@@ -27,6 +28,8 @@
27	28	#include <sound/dmaengine_pcm.h>
28	29
29	30	#include "rockchip_i2s_tdm.h"
	31	+#include "rockchip_dlp_pcm.h"
	32	+#include "rockchip_utils.h"
30	33
31	34	#define DRV_NAME "rockchip-i2s-tdm"
32	35
..	..	@@ -34,11 +37,45 @@
34	37	#define HAVE_SYNC_RESET
35	38	#endif
36	39
	40	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	41	+/*
	42	+ * Example: RK3588
	43	+ *
	44	+ * Use I2S2_2CH as Clk-Gen to serve TDM_MULTI_LANES
	45	+ *
	46	+ * I2S2_2CH ----> BCLK,I2S_LRCK --------> I2S0_8CH_TX (Slave TRCM-TXONLY)
	47	+ * \|
	48	+ * \|--------> BCLK,TDM_SYNC --------> TDM Device (Slave)
	49	+ *
	50	+ * Note:
	51	+ *
	52	+ * I2S2_2CH_MCLK: BCLK
	53	+ * I2S2_2CH_SCLK: I2S_LRCK (GPIO2_B7)
	54	+ * I2S2_2CH_LRCK: TDM_SYNC (GPIO2_C0)
	55	+ *
	56	+ */
	57	+
	58	+#define CLK_MAX_COUNT 1000
	59	+#define NSAMPLES 4
	60	+#define XFER_EN 0x3
	61	+#define XFER_DIS 0x0
	62	+#define CKR_V(m, r, t) ((m - 1) << 16 \| (r - 1) << 8 \| (t - 1) << 0)
	63	+#define I2S_XCR_IBM_V(v) ((v) & I2S_TXCR_IBM_MASK)
	64	+#define I2S_XCR_IBM_NORMAL I2S_TXCR_IBM_NORMAL
	65	+#define I2S_XCR_IBM_LSJM I2S_TXCR_IBM_LSJM
	66	+#endif
	67	+
37	68	#define DEFAULT_MCLK_FS 256
	69	+#define DEFAULT_FS 48000
38	70	#define CH_GRP_MAX 4 /* The max channel 8 / 2 */
39	71	#define MULTIPLEX_CH_MAX 10
40	72	#define CLK_PPM_MIN (-1000)
41	73	#define CLK_PPM_MAX (1000)
	74	+#define MAXBURST_PER_FIFO 8
	75	+#define WAIT_TIME_MS_MAX 10000
	76	+
	77	+#define QUIRK_ALWAYS_ON BIT(0)
	78	+#define QUIRK_HDMI_PATH BIT(1)
42	79
43	80	struct txrx_config {
44	81	u32 addr;
..	..	@@ -79,8 +116,12 @@
79	116	struct regmap *grf;
80	117	struct snd_dmaengine_dai_dma_data capture_dma_data;
81	118	struct snd_dmaengine_dai_dma_data playback_dma_data;
	119	+ struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
	120	+ unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
82	121	struct reset_control *tx_reset;
83	122	struct reset_control *rx_reset;
	123	+ struct pinctrl *pinctrl;
	124	+ struct pinctrl_state *clk_state;
84	125	const struct rk_i2s_soc_data *soc_data;
85	126	#ifdef HAVE_SYNC_RESET
86	127	void __iomem *cru_base;
..	..	@@ -92,6 +133,7 @@
92	133	bool mclk_calibrate;
93	134	bool tdm_mode;
94	135	bool tdm_fsync_half_frame;
	136	+ bool is_dma_active[SNDRV_PCM_STREAM_LAST + 1];
95	137	unsigned int mclk_rx_freq;
96	138	unsigned int mclk_tx_freq;
97	139	unsigned int mclk_root0_freq;
..	..	@@ -102,9 +144,34 @@
102	144	unsigned int clk_trcm;
103	145	unsigned int i2s_sdis[CH_GRP_MAX];
104	146	unsigned int i2s_sdos[CH_GRP_MAX];
	147	+ unsigned int quirks;
	148	+ unsigned int lrck_ratio;
105	149	int clk_ppm;
106	150	atomic_t refcount;
107	151	spinlock_t lock; /* xfer lock */
	152	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	153	+ struct snd_soc_dai *clk_src_dai;
	154	+ struct gpio_desc *i2s_lrck_gpio;
	155	+ struct gpio_desc *tdm_fsync_gpio;
	156	+ unsigned int tx_lanes;
	157	+ unsigned int rx_lanes;
	158	+ void __iomem *clk_src_base;
	159	+ bool is_tdm_multi_lanes;
	160	+#endif
	161	+};
	162	+
	163	+static struct i2s_of_quirks {
	164	+ char *quirk;
	165	+ int id;
	166	+} of_quirks[] = {
	167	+ {
	168	+ .quirk = "rockchip,always-on",
	169	+ .id = QUIRK_ALWAYS_ON,
	170	+ },
	171	+ {
	172	+ .quirk = "rockchip,hdmi-path",
	173	+ .id = QUIRK_HDMI_PATH,
	174	+ },
108	175	};
109	176
110	177	static int to_ch_num(unsigned int val)
..	..	@@ -134,10 +201,23 @@
134	201	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
135	202
136	203	regcache_cache_only(i2s_tdm->regmap, true);
137		- if (!IS_ERR(i2s_tdm->mclk_tx))
138		- clk_disable_unprepare(i2s_tdm->mclk_tx);
139		- if (!IS_ERR(i2s_tdm->mclk_rx))
140		- clk_disable_unprepare(i2s_tdm->mclk_rx);
	204	+
	205	+ clk_disable_unprepare(i2s_tdm->mclk_tx);
	206	+ clk_disable_unprepare(i2s_tdm->mclk_rx);
	207	+
	208	+ pinctrl_pm_select_idle_state(dev);
	209	+
	210	+ return 0;
	211	+}
	212	+
	213	+static int rockchip_i2s_tdm_pinctrl_select_clk_state(struct device *dev)
	214	+{
	215	+ struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
	216	+
	217	+ if (IS_ERR_OR_NULL(i2s_tdm->pinctrl) \|\| !i2s_tdm->clk_state)
	218	+ return 0;
	219	+
	220	+ pinctrl_select_state(i2s_tdm->pinctrl, i2s_tdm->clk_state);
141	221
142	222	return 0;
143	223	}
..	..	@@ -147,28 +227,71 @@
147	227	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
148	228	int ret;
149	229
150		- if (!IS_ERR(i2s_tdm->mclk_tx))
151		- clk_prepare_enable(i2s_tdm->mclk_tx);
152		- if (!IS_ERR(i2s_tdm->mclk_rx))
153		- clk_prepare_enable(i2s_tdm->mclk_rx);
	230	+ /*
	231	+ * pinctrl default state is invoked by ASoC framework, so,
	232	+ * we just handle clk state here if DT assigned.
	233	+ */
	234	+ if (i2s_tdm->is_master_mode)
	235	+ rockchip_i2s_tdm_pinctrl_select_clk_state(dev);
	236	+
	237	+ ret = clk_prepare_enable(i2s_tdm->mclk_tx);
	238	+ if (ret)
	239	+ goto err_mclk_tx;
	240	+
	241	+ ret = clk_prepare_enable(i2s_tdm->mclk_rx);
	242	+ if (ret)
	243	+ goto err_mclk_rx;
154	244
155	245	regcache_cache_only(i2s_tdm->regmap, false);
156	246	regcache_mark_dirty(i2s_tdm->regmap);
157		-
158	247	ret = regcache_sync(i2s_tdm->regmap);
159		- if (ret) {
160		- if (!IS_ERR(i2s_tdm->mclk_tx))
161		- clk_disable_unprepare(i2s_tdm->mclk_tx);
162		- if (!IS_ERR(i2s_tdm->mclk_rx))
163		- clk_disable_unprepare(i2s_tdm->mclk_rx);
164		- }
	248	+ if (ret)
	249	+ goto err_regmap;
165	250
	251	+ /*
	252	+ * should be placed after regcache sync done to back
	253	+ * to the slave mode and then enable clk state.
	254	+ */
	255	+ if (!i2s_tdm->is_master_mode)
	256	+ rockchip_i2s_tdm_pinctrl_select_clk_state(dev);
	257	+
	258	+ return 0;
	259	+
	260	+err_regmap:
	261	+ clk_disable_unprepare(i2s_tdm->mclk_rx);
	262	+err_mclk_rx:
	263	+ clk_disable_unprepare(i2s_tdm->mclk_tx);
	264	+err_mclk_tx:
166	265	return ret;
167	266	}
168	267
169	268	static inline struct rk_i2s_tdm_dev to_info(struct snd_soc_dai dai)
170	269	{
171	270	return snd_soc_dai_get_drvdata(dai);
	271	+}
	272	+
	273	+static inline bool is_stream_active(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	274	+{
	275	+ unsigned int val;
	276	+
	277	+ regmap_read(i2s_tdm->regmap, I2S_XFER, &val);
	278	+
	279	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
	280	+ return (val & I2S_XFER_TXS_START);
	281	+ else
	282	+ return (val & I2S_XFER_RXS_START);
	283	+}
	284	+
	285	+static inline bool is_dma_active(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	286	+{
	287	+ unsigned int val;
	288	+
	289	+ regmap_read(i2s_tdm->regmap, I2S_DMACR, &val);
	290	+
	291	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
	292	+ return (val & I2S_DMACR_TDE_MASK);
	293	+ else
	294	+ return (val & I2S_DMACR_RDE_MASK);
172	295	}
173	296
174	297	#ifdef HAVE_SYNC_RESET
..	..	@@ -180,7 +303,7 @@
180	303	#define writeq(v,c) ({ __iowmb(); __raw_writeq((__force u64) cpu_to_le64(v), c); })
181	304	#endif
182	305
183		-static void rockchip_snd_xfer_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
	306	+static void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
184	307	{
185	308	int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
186	309	void __iomem cru_reset, addr;
..	..	@@ -229,7 +352,7 @@
229	352	writeq(val, addr);
230	353	break;
231	354	}
232		- /* fall through */
	355	+ fallthrough;
233	356	default:
234	357	local_irq_save(flags);
235	358	writel(BIT(tx_offset) \| (BIT(tx_offset) << 16),
..	..	@@ -243,7 +366,7 @@
243	366	udelay(10);
244	367	}
245	368
246		-static void rockchip_snd_xfer_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
	369	+static void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
247	370	{
248	371	int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
249	372	void __iomem cru_reset, addr;
..	..	@@ -291,7 +414,7 @@
291	414	writeq(val, addr);
292	415	break;
293	416	}
294		- /* fall through */
	417	+ fallthrough;
295	418	default:
296	419	local_irq_save(flags);
297	420	writel((BIT(tx_offset) << 16),
..	..	@@ -309,94 +432,26 @@
309	432	* make sure both tx and rx are reset at the same time for sync lrck
310	433	* when clk_trcm > 0
311	434	*/
312		-static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
	435	+static void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
313	436	{
314		- rockchip_snd_xfer_reset_assert(i2s_tdm);
315		- rockchip_snd_xfer_reset_deassert(i2s_tdm);
	437	+ rockchip_i2s_tdm_reset_assert(i2s_tdm);
	438	+ rockchip_i2s_tdm_reset_deassert(i2s_tdm);
316	439	}
317	440	#else
318		-static inline void rockchip_snd_xfer_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
	441	+static inline void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
319	442	{
320	443	}
321		-static inline void rockchip_snd_xfer_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
	444	+static inline void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
322	445	{
323	446	}
324		-static inline void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
	447	+static inline void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
325	448	{
326	449	}
327	450	#endif
328	451
329		-/* only used when clk_trcm > 0 */
330		-static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
331		- struct snd_soc_dai *dai, int on)
	452	+static void rockchip_i2s_tdm_reset(struct reset_control *rc)
332	453	{
333		- struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
334		- unsigned int val = 0;
335		- unsigned long flags;
336		- int retry = 10;
337		-
338		- spin_lock_irqsave(&i2s_tdm->lock, flags);
339		- if (on) {
340		- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
342		- I2S_DMACR_TDE_ENABLE,
343		- I2S_DMACR_TDE_ENABLE);
344		- else
345		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
346		- I2S_DMACR_RDE_ENABLE,
347		- I2S_DMACR_RDE_ENABLE);
348		-
349		- if (atomic_inc_return(&i2s_tdm->refcount) == 1) {
350		- rockchip_snd_xfer_reset_assert(i2s_tdm);
351		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
352		- I2S_XFER_TXS_START \|
353		- I2S_XFER_RXS_START,
354		- I2S_XFER_TXS_START \|
355		- I2S_XFER_RXS_START);
356		- rockchip_snd_xfer_reset_deassert(i2s_tdm);
357		- }
358		- } else {
359		- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
360		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
361		- I2S_DMACR_TDE_ENABLE,
362		- I2S_DMACR_TDE_DISABLE);
363		- else
364		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
365		- I2S_DMACR_RDE_ENABLE,
366		- I2S_DMACR_RDE_DISABLE);
367		-
368		- if (atomic_dec_and_test(&i2s_tdm->refcount)) {
369		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
370		- I2S_XFER_TXS_START \|
371		- I2S_XFER_RXS_START,
372		- I2S_XFER_TXS_STOP \|
373		- I2S_XFER_RXS_STOP);
374		-
375		- udelay(150);
376		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
377		- I2S_CLR_TXC \| I2S_CLR_RXC,
378		- I2S_CLR_TXC \| I2S_CLR_RXC);
379		-
380		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
381		-
382		- /* Should wait for clear operation to finish */
383		- while (val) {
384		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
385		- retry--;
386		- if (!retry) {
387		- dev_info(i2s_tdm->dev, "reset txrx\n");
388		- rockchip_snd_xfer_sync_reset(i2s_tdm);
389		- break;
390		- }
391		- }
392		- }
393		- }
394		- spin_unlock_irqrestore(&i2s_tdm->lock, flags);
395		-}
396		-
397		-static void rockchip_snd_reset(struct reset_control *rc)
398		-{
399		- if (IS_ERR(rc))
	454	+ if (IS_ERR_OR_NULL(rc))
400	455	return;
401	456
402	457	reset_control_assert(rc);
..	..	@@ -407,92 +462,554 @@
407	462	udelay(10);
408	463	}
409	464
410		-static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
	465	+static int rockchip_i2s_tdm_clear(struct rk_i2s_tdm_dev *i2s_tdm,
	466	+ unsigned int clr)
411	467	{
	468	+ struct reset_control *rst = NULL;
412	469	unsigned int val = 0;
413		- int retry = 10;
	470	+ int ret = 0;
414	471
415		- if (on) {
416		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
417		- I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
	472	+ switch (clr) {
	473	+ case I2S_CLR_TXC:
	474	+ rst = i2s_tdm->tx_reset;
	475	+ break;
	476	+ case I2S_CLR_RXC:
	477	+ rst = i2s_tdm->rx_reset;
	478	+ break;
	479	+ case I2S_CLR_TXC \| I2S_CLR_RXC:
	480	+ break;
	481	+ default:
	482	+ return -EINVAL;
	483	+ }
418	484
419		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
420		- I2S_XFER_TXS_START,
421		- I2S_XFER_TXS_START);
	485	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
	486	+ ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
	487	+ !(val & clr), 10, 100);
	488	+ if (ret == 0)
	489	+ return 0;
	490	+
	491	+ /*
	492	+ * Workaround for FIFO clear on SLAVE mode:
	493	+ *
	494	+ * A Suggest to do reset hclk domain and then do mclk
	495	+ * domain, especially for SLAVE mode without CLK in.
	496	+ * at last, recovery regmap config.
	497	+ *
	498	+ * B Suggest to switch to MASTER, and then do FIFO clr,
	499	+ * at last, bring back to SLAVE.
	500	+ *
	501	+ * Now we choose plan B here.
	502	+ */
	503	+ if (!i2s_tdm->is_master_mode)
	504	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	505	+ I2S_CKR_MSS_MASK, I2S_CKR_MSS_MASTER);
	506	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
	507	+ ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
	508	+ !(val & clr), 10, 100);
	509	+ if (!i2s_tdm->is_master_mode)
	510	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	511	+ I2S_CKR_MSS_MASK, I2S_CKR_MSS_SLAVE);
	512	+
	513	+ if (ret < 0) {
	514	+ dev_warn(i2s_tdm->dev, "failed to clear %u on %s mode\n",
	515	+ clr, i2s_tdm->is_master_mode ? "master" : "slave");
	516	+ goto reset;
	517	+ }
	518	+
	519	+ return 0;
	520	+
	521	+reset:
	522	+ if (i2s_tdm->clk_trcm)
	523	+ rockchip_i2s_tdm_sync_reset(i2s_tdm);
	524	+ else
	525	+ rockchip_i2s_tdm_reset(rst);
	526	+
	527	+ return 0;
	528	+}
	529	+
	530	+/*
	531	+ * HDMI controller ignores the first FRAME_SYNC cycle, Lost one frame is no big deal
	532	+ * for LPCM, but it does matter for Bitstream (NLPCM/HBR), So, padding one frame
	533	+ * before xfer the real data to fix it.
	534	+ */
	535	+static void rockchip_i2s_tdm_tx_fifo_padding(struct rk_i2s_tdm_dev *i2s_tdm, bool en)
	536	+{
	537	+ unsigned int val, w, c, i;
	538	+
	539	+ if (!en)
	540	+ return;
	541	+
	542	+ regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
	543	+ w = ((val & I2S_TXCR_VDW_MASK) >> I2S_TXCR_VDW_SHIFT) + 1;
	544	+ c = to_ch_num(val & I2S_TXCR_CSR_MASK) * w / 32;
	545	+
	546	+ for (i = 0; i < c; i++)
	547	+ regmap_write(i2s_tdm->regmap, I2S_TXDR, 0x0);
	548	+}
	549	+
	550	+static void rockchip_i2s_tdm_fifo_xrun_detect(struct rk_i2s_tdm_dev *i2s_tdm,
	551	+ int stream, bool en)
	552	+{
	553	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	554	+ /* clear irq status which was asserted before TXUIE enabled */
	555	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	556	+ I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
	557	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	558	+ I2S_INTCR_TXUIE_MASK,
	559	+ I2S_INTCR_TXUIE(en));
422	560	} else {
423		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
424		- I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
425		-
426		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
427		- I2S_XFER_TXS_START,
428		- I2S_XFER_TXS_STOP);
429		-
430		- udelay(150);
431		- if (i2s_tdm->is_master_mode) {
432		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
433		- I2S_CLR_TXC,
434		- I2S_CLR_TXC);
435		-
436		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
437		-
438		- /* Should wait for clear operation to finish */
439		- while (val) {
440		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
441		- retry--;
442		- if (!retry) {
443		- dev_warn(i2s_tdm->dev, "reset tx\n");
444		- rockchip_snd_reset(i2s_tdm->tx_reset);
445		- break;
446		- }
447		- }
448		- } else {
449		- rockchip_snd_reset(i2s_tdm->tx_reset);
450		- }
	561	+ /* clear irq status which was asserted before RXOIE enabled */
	562	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	563	+ I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
	564	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	565	+ I2S_INTCR_RXOIE_MASK,
	566	+ I2S_INTCR_RXOIE(en));
451	567	}
452	568	}
453	569
454		-static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
	570	+static void rockchip_i2s_tdm_dma_ctrl(struct rk_i2s_tdm_dev *i2s_tdm,
	571	+ int stream, bool en)
455	572	{
456		- unsigned int val = 0;
457		- int retry = 10;
	573	+ if (!en)
	574	+ rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 0);
458	575
459		- if (on) {
	576	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	577	+ if (i2s_tdm->quirks & QUIRK_HDMI_PATH)
	578	+ rockchip_i2s_tdm_tx_fifo_padding(i2s_tdm, en);
	579	+
460	580	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
461		- I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
462		-
463		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
464		- I2S_XFER_RXS_START,
465		- I2S_XFER_RXS_START);
	581	+ I2S_DMACR_TDE_MASK,
	582	+ I2S_DMACR_TDE(en));
	583	+ /*
	584	+ * Explicitly delay 1 usec for dma to fill FIFO,
	585	+ * though there was a implied HW delay that around
	586	+ * half LRCK cycle (e.g. 2.6us@192k) from XFER-start
	587	+ * to FIFO-pop.
	588	+ *
	589	+ * 1 usec is enough to fill at lease 4 entry each FIFO
	590	+ * @192k 8ch 32bit situation.
	591	+ */
	592	+ udelay(1);
466	593	} else {
467	594	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
468		- I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
469		-
470		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
471		- I2S_XFER_RXS_START,
472		- I2S_XFER_RXS_STOP);
473		-
474		- udelay(150);
475		- if (i2s_tdm->is_master_mode) {
476		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
477		- I2S_CLR_RXC,
478		- I2S_CLR_RXC);
479		-
480		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
481		-
482		- /* Should wait for clear operation to finish */
483		- while (val) {
484		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
485		- retry--;
486		- if (!retry) {
487		- dev_warn(i2s_tdm->dev, "reset rx\n");
488		- rockchip_snd_reset(i2s_tdm->rx_reset);
489		- break;
490		- }
491		- }
492		- } else {
493		- rockchip_snd_reset(i2s_tdm->rx_reset);
494		- }
	595	+ I2S_DMACR_RDE_MASK,
	596	+ I2S_DMACR_RDE(en));
495	597	}
	598	+
	599	+ if (en)
	600	+ rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 1);
	601	+}
	602	+
	603	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	604	+static const char * const tx_lanes_text[] = { "Auto", "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
	605	+static const char * const rx_lanes_text[] = { "Auto", "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
	606	+static const struct soc_enum tx_lanes_enum =
	607	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
	608	+static const struct soc_enum rx_lanes_enum =
	609	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
	610	+
	611	+static int rockchip_i2s_tdm_tx_lanes_get(struct snd_kcontrol *kcontrol,
	612	+ struct snd_ctl_elem_value *ucontrol)
	613	+{
	614	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	615	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	616	+
	617	+ ucontrol->value.enumerated.item[0] = i2s_tdm->tx_lanes;
	618	+
	619	+ return 0;
	620	+}
	621	+
	622	+static int rockchip_i2s_tdm_tx_lanes_put(struct snd_kcontrol *kcontrol,
	623	+ struct snd_ctl_elem_value *ucontrol)
	624	+{
	625	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	626	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	627	+ int num;
	628	+
	629	+ num = ucontrol->value.enumerated.item[0];
	630	+ if (num >= ARRAY_SIZE(tx_lanes_text))
	631	+ return -EINVAL;
	632	+
	633	+ i2s_tdm->tx_lanes = num;
	634	+
	635	+ return 1;
	636	+}
	637	+
	638	+static int rockchip_i2s_tdm_rx_lanes_get(struct snd_kcontrol *kcontrol,
	639	+ struct snd_ctl_elem_value *ucontrol)
	640	+{
	641	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	642	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	643	+
	644	+ ucontrol->value.enumerated.item[0] = i2s_tdm->rx_lanes;
	645	+
	646	+ return 0;
	647	+}
	648	+
	649	+static int rockchip_i2s_tdm_rx_lanes_put(struct snd_kcontrol *kcontrol,
	650	+ struct snd_ctl_elem_value *ucontrol)
	651	+{
	652	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	653	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	654	+ int num;
	655	+
	656	+ num = ucontrol->value.enumerated.item[0];
	657	+ if (num >= ARRAY_SIZE(rx_lanes_text))
	658	+ return -EINVAL;
	659	+
	660	+ i2s_tdm->rx_lanes = num;
	661	+
	662	+ return 1;
	663	+}
	664	+
	665	+static int rockchip_i2s_tdm_get_lanes(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	666	+{
	667	+ unsigned int lanes = 1;
	668	+
	669	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	670	+ if (i2s_tdm->tx_lanes)
	671	+ lanes = i2s_tdm->tx_lanes;
	672	+ } else {
	673	+ if (i2s_tdm->rx_lanes)
	674	+ lanes = i2s_tdm->rx_lanes;
	675	+ }
	676	+
	677	+ return lanes;
	678	+}
	679	+
	680	+static struct snd_soc_dai rockchip_i2s_tdm_find_dai(struct device_node np)
	681	+{
	682	+ struct snd_soc_dai_link_component dai_component = { 0 };
	683	+
	684	+ dai_component.of_node = np;
	685	+
	686	+ return snd_soc_find_dai_with_mutex(&dai_component);
	687	+}
	688	+
	689	+static int rockchip_i2s_tdm_multi_lanes_set_clk(struct snd_pcm_substream *substream,
	690	+ struct snd_pcm_hw_params *params,
	691	+ struct snd_soc_dai *cpu_dai)
	692	+{
	693	+ struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
	694	+ struct snd_soc_dai *dai = i2s_tdm->clk_src_dai;
	695	+ unsigned int div, mclk_rate;
	696	+ unsigned int lanes, ch_per_lane;
	697	+
	698	+ lanes = rockchip_i2s_tdm_get_lanes(i2s_tdm, substream->stream);
	699	+ ch_per_lane = params_channels(params) / lanes;
	700	+ mclk_rate = ch_per_lane * params_rate(params) * 32;
	701	+ div = ch_per_lane / 2;
	702	+
	703	+ /* Do nothing when use external clk src */
	704	+ if (dai && dai->driver->ops) {
	705	+ if (dai->driver->ops->set_sysclk)
	706	+ dai->driver->ops->set_sysclk(dai, substream->stream, mclk_rate, 0);
	707	+
	708	+ writel(XFER_DIS, i2s_tdm->clk_src_base + I2S_XFER);
	709	+ writel(CKR_V(64, div, div), i2s_tdm->clk_src_base + I2S_CKR);
	710	+ writel(XFER_EN, i2s_tdm->clk_src_base + I2S_XFER);
	711	+ }
	712	+
	713	+ i2s_tdm->lrck_ratio = div;
	714	+ i2s_tdm->mclk_tx_freq = mclk_rate;
	715	+ i2s_tdm->mclk_rx_freq = mclk_rate;
	716	+
	717	+ return 0;
	718	+}
	719	+
	720	+static inline int tdm_multi_lanes_clk_assert_h(const struct gpio_desc *desc)
	721	+{
	722	+ int cnt = CLK_MAX_COUNT;
	723	+
	724	+ while (gpiod_get_raw_value(desc) && --cnt)
	725	+ ;
	726	+
	727	+ return cnt;
	728	+}
	729	+
	730	+static inline int tdm_multi_lanes_clk_assert_l(const struct gpio_desc *desc)
	731	+{
	732	+ int cnt = CLK_MAX_COUNT;
	733	+
	734	+ while (!gpiod_get_raw_value(desc) && --cnt)
	735	+ ;
	736	+
	737	+ return cnt;
	738	+}
	739	+
	740	+static inline bool rockchip_i2s_tdm_clk_valid(struct rk_i2s_tdm_dev *i2s_tdm)
	741	+{
	742	+ int dc_h = CLK_MAX_COUNT, dc_l = CLK_MAX_COUNT;
	743	+
	744	+ /*
	745	+ * TBD: optimize debounce and get value
	746	+ *
	747	+ * debounce at least one cycle found, otherwise, the clk ref maybe
	748	+ * not on the fly.
	749	+ */
	750	+
	751	+ /* check HIGH-Level */
	752	+ dc_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	753	+ if (!dc_h)
	754	+ return false;
	755	+
	756	+ /* check LOW-Level */
	757	+ dc_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	758	+ if (!dc_l)
	759	+ return false;
	760	+
	761	+ /* check HIGH-Level */
	762	+ dc_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
	763	+ if (!dc_h)
	764	+ return false;
	765	+
	766	+ /* check LOW-Level */
	767	+ dc_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
	768	+ if (!dc_l)
	769	+ return false;
	770	+
	771	+ return true;
	772	+}
	773	+
	774	+static void __maybe_unused rockchip_i2s_tdm_gpio_clk_meas(struct rk_i2s_tdm_dev *i2s_tdm,
	775	+ const struct gpio_desc *desc,
	776	+ const char *name)
	777	+{
	778	+ int h[NSAMPLES], l[NSAMPLES], i;
	779	+
	780	+ dev_dbg(i2s_tdm->dev, "%s:\n", name);
	781	+
	782	+ if (!rockchip_i2s_tdm_clk_valid(i2s_tdm))
	783	+ return;
	784	+
	785	+ for (i = 0; i < NSAMPLES; i++) {
	786	+ h[i] = tdm_multi_lanes_clk_assert_h(desc);
	787	+ l[i] = tdm_multi_lanes_clk_assert_l(desc);
	788	+ }
	789	+
	790	+ for (i = 0; i < NSAMPLES; i++)
	791	+ dev_dbg(i2s_tdm->dev, "H[%d]: %2d, L[%d]: %2d\n",
	792	+ i, CLK_MAX_COUNT - h[i], i, CLK_MAX_COUNT - l[i]);
	793	+}
	794	+
	795	+static int rockchip_i2s_tdm_multi_lanes_start(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	796	+{
	797	+ unsigned int tdm_h = 0, tdm_l = 0, i2s_h = 0, i2s_l = 0;
	798	+ unsigned int msk, val, reg, fmt;
	799	+ unsigned long flags;
	800	+
	801	+ if (!i2s_tdm->tdm_fsync_gpio \|\| !i2s_tdm->i2s_lrck_gpio)
	802	+ return -ENOSYS;
	803	+
	804	+ if (i2s_tdm->lrck_ratio != 4 && i2s_tdm->lrck_ratio != 8)
	805	+ return -EINVAL;
	806	+
	807	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	808	+ msk = I2S_XFER_TXS_MASK;
	809	+ val = I2S_XFER_TXS_START;
	810	+ reg = I2S_TXCR;
	811	+ } else {
	812	+ msk = I2S_XFER_RXS_MASK;
	813	+ val = I2S_XFER_RXS_START;
	814	+ reg = I2S_RXCR;
	815	+ }
	816	+
	817	+ regmap_read(i2s_tdm->regmap, reg, &fmt);
	818	+ fmt = I2S_XCR_IBM_V(fmt);
	819	+
	820	+ local_irq_save(flags);
	821	+
	822	+ if (!rockchip_i2s_tdm_clk_valid(i2s_tdm)) {
	823	+ local_irq_restore(flags);
	824	+ dev_err(i2s_tdm->dev, "Invalid LRCK / FSYNC measured by ref IO\n");
	825	+ return -EINVAL;
	826	+ }
	827	+
	828	+ switch (fmt) {
	829	+ case I2S_XCR_IBM_NORMAL:
	830	+ tdm_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
	831	+ tdm_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
	832	+
	833	+ if (i2s_tdm->lrck_ratio == 8) {
	834	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	835	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	836	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	837	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	838	+ }
	839	+
	840	+ i2s_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	841	+
	842	+ if (stream == SNDRV_PCM_STREAM_CAPTURE)
	843	+ i2s_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	844	+ break;
	845	+ case I2S_XCR_IBM_LSJM:
	846	+ tdm_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
	847	+ tdm_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
	848	+
	849	+ if (i2s_tdm->lrck_ratio == 8) {
	850	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	851	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	852	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	853	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	854	+ }
	855	+
	856	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	857	+
	858	+ i2s_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	859	+ i2s_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	860	+ break;
	861	+ default:
	862	+ local_irq_restore(flags);
	863	+ return -EINVAL;
	864	+ }
	865	+
	866	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER, msk, val);
	867	+ local_irq_restore(flags);
	868	+
	869	+ dev_dbg(i2s_tdm->dev, "STREAM[%d]: TDM-H: %d, TDM-L: %d, I2S-H: %d, I2S-L: %d\n", stream,
	870	+ CLK_MAX_COUNT - tdm_h, CLK_MAX_COUNT - tdm_l,
	871	+ CLK_MAX_COUNT - i2s_h, CLK_MAX_COUNT - i2s_l);
	872	+
	873	+ return 0;
	874	+}
	875	+#endif
	876	+
	877	+static void rockchip_i2s_tdm_xfer_start(struct rk_i2s_tdm_dev *i2s_tdm,
	878	+ int stream)
	879	+{
	880	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	881	+ if (i2s_tdm->is_tdm_multi_lanes) {
	882	+ if (rockchip_i2s_tdm_multi_lanes_start(i2s_tdm, stream) != -ENOSYS)
	883	+ return;
	884	+ }
	885	+#endif
	886	+ if (i2s_tdm->clk_trcm) {
	887	+ rockchip_i2s_tdm_reset_assert(i2s_tdm);
	888	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
	889	+ I2S_XFER_TXS_MASK \|
	890	+ I2S_XFER_RXS_MASK,
	891	+ I2S_XFER_TXS_START \|
	892	+ I2S_XFER_RXS_START);
	893	+ rockchip_i2s_tdm_reset_deassert(i2s_tdm);
	894	+ } else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	895	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
	896	+ I2S_XFER_TXS_MASK,
	897	+ I2S_XFER_TXS_START);
	898	+ } else {
	899	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
	900	+ I2S_XFER_RXS_MASK,
	901	+ I2S_XFER_RXS_START);
	902	+ }
	903	+}
	904	+
	905	+static void rockchip_i2s_tdm_xfer_stop(struct rk_i2s_tdm_dev *i2s_tdm,
	906	+ int stream, bool force)
	907	+{
	908	+ unsigned int msk, val, clr;
	909	+
	910	+ if (i2s_tdm->quirks & QUIRK_ALWAYS_ON && !force)
	911	+ return;
	912	+
	913	+ if (i2s_tdm->clk_trcm) {
	914	+ msk = I2S_XFER_TXS_MASK \| I2S_XFER_RXS_MASK;
	915	+ val = I2S_XFER_TXS_STOP \| I2S_XFER_RXS_STOP;
	916	+ clr = I2S_CLR_TXC \| I2S_CLR_RXC;
	917	+ } else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	918	+ msk = I2S_XFER_TXS_MASK;
	919	+ val = I2S_XFER_TXS_STOP;
	920	+ clr = I2S_CLR_TXC;
	921	+ } else {
	922	+ msk = I2S_XFER_RXS_MASK;
	923	+ val = I2S_XFER_RXS_STOP;
	924	+ clr = I2S_CLR_RXC;
	925	+ }
	926	+
	927	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER, msk, val);
	928	+
	929	+ /* delay for LRCK signal integrity */
	930	+ udelay(150);
	931	+
	932	+ rockchip_i2s_tdm_clear(i2s_tdm, clr);
	933	+}
	934	+
	935	+static void rockchip_i2s_tdm_xfer_trcm_start(struct rk_i2s_tdm_dev *i2s_tdm)
	936	+{
	937	+ unsigned long flags;
	938	+
	939	+ spin_lock_irqsave(&i2s_tdm->lock, flags);
	940	+ if (atomic_inc_return(&i2s_tdm->refcount) == 1)
	941	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, 0);
	942	+ spin_unlock_irqrestore(&i2s_tdm->lock, flags);
	943	+}
	944	+
	945	+static void rockchip_i2s_tdm_xfer_trcm_stop(struct rk_i2s_tdm_dev *i2s_tdm)
	946	+{
	947	+ unsigned long flags;
	948	+
	949	+ spin_lock_irqsave(&i2s_tdm->lock, flags);
	950	+ if (atomic_dec_and_test(&i2s_tdm->refcount))
	951	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, 0, false);
	952	+ spin_unlock_irqrestore(&i2s_tdm->lock, flags);
	953	+}
	954	+
	955	+static void rockchip_i2s_tdm_trcm_pause(struct snd_pcm_substream *substream,
	956	+ struct rk_i2s_tdm_dev *i2s_tdm)
	957	+{
	958	+ int stream = substream->stream;
	959	+ int bstream = SNDRV_PCM_STREAM_LAST - stream;
	960	+
	961	+ /* store the current state, prepare for resume if necessary */
	962	+ i2s_tdm->is_dma_active[bstream] = is_dma_active(i2s_tdm, bstream);
	963	+
	964	+ /* disable dma for both tx and rx */
	965	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
	966	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 0);
	967	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, bstream, true);
	968	+}
	969	+
	970	+static void rockchip_i2s_tdm_trcm_resume(struct snd_pcm_substream *substream,
	971	+ struct rk_i2s_tdm_dev *i2s_tdm)
	972	+{
	973	+ int bstream = SNDRV_PCM_STREAM_LAST - substream->stream;
	974	+
	975	+ /*
	976	+ * just resume bstream, because current stream will be
	977	+ * startup in the trigger-cmd-START
	978	+ */
	979	+ if (i2s_tdm->is_dma_active[bstream])
	980	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 1);
	981	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, bstream);
	982	+}
	983	+
	984	+static void rockchip_i2s_tdm_start(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	985	+{
	986	+ /*
	987	+ * On HDMI-PATH-ALWAYS-ON situation, we almost keep XFER always on,
	988	+ * so, for new data start, suggested to STOP-CLEAR-START to make sure
	989	+ * data aligned.
	990	+ */
	991	+ if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
	992	+ (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
	993	+ (stream == SNDRV_PCM_STREAM_PLAYBACK)) {
	994	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
	995	+ }
	996	+
	997	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 1);
	998	+
	999	+ if (i2s_tdm->clk_trcm)
	1000	+ rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
	1001	+ else
	1002	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, stream);
	1003	+}
	1004	+
	1005	+static void rockchip_i2s_tdm_stop(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	1006	+{
	1007	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
	1008	+
	1009	+ if (i2s_tdm->clk_trcm)
	1010	+ rockchip_i2s_tdm_xfer_trcm_stop(i2s_tdm);
	1011	+ else
	1012	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, false);
496	1013	}
497	1014
498	1015	static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
..	..	@@ -513,6 +1030,19 @@
513	1030	case SND_SOC_DAIFMT_CBM_CFM:
514	1031	val = I2S_CKR_MSS_SLAVE;
515	1032	i2s_tdm->is_master_mode = false;
	1033	+ /*
	1034	+ * TRCM require TX/RX enabled at the same time, or need the one
	1035	+ * which provide clk enabled at first for master mode.
	1036	+ *
	1037	+ * It is quite a different for slave mode which does not have
	1038	+ * these restrictions, because the BCLK / LRCK are provided by
	1039	+ * external master devices.
	1040	+ *
	1041	+ * So, we just set the right clk path value on TRCM register on
	1042	+ * stage probe and then drop the trcm value to make TX / RX work
	1043	+ * independently.
	1044	+ */
	1045	+ i2s_tdm->clk_trcm = 0;
516	1046	break;
517	1047	default:
518	1048	ret = -EINVAL;
..	..	@@ -659,72 +1189,6 @@
659	1189	return ret;
660	1190	}
661	1191
662		-static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
663		- struct rk_i2s_tdm_dev *i2s_tdm)
664		-{
665		- int stream;
666		- unsigned int val = 0;
667		- int retry = 10;
668		-
669		- stream = SNDRV_PCM_STREAM_LAST - substream->stream;
670		- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
671		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
672		- I2S_DMACR_TDE_ENABLE,
673		- I2S_DMACR_TDE_DISABLE);
674		- else
675		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
676		- I2S_DMACR_RDE_ENABLE,
677		- I2S_DMACR_RDE_DISABLE);
678		-
679		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
680		- I2S_XFER_TXS_START \|
681		- I2S_XFER_RXS_START,
682		- I2S_XFER_TXS_STOP \|
683		- I2S_XFER_RXS_STOP);
684		-
685		- udelay(150);
686		- regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
687		- I2S_CLR_TXC \| I2S_CLR_RXC,
688		- I2S_CLR_TXC \| I2S_CLR_RXC);
689		-
690		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
691		-
692		- /* Should wait for clear operation to finish */
693		- while (val) {
694		- regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
695		- retry--;
696		- if (!retry) {
697		- dev_info(i2s_tdm->dev, "reset txrx\n");
698		- rockchip_snd_xfer_sync_reset(i2s_tdm);
699		- break;
700		- }
701		- }
702		-}
703		-
704		-static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
705		- struct rk_i2s_tdm_dev *i2s_tdm)
706		-{
707		- int stream;
708		-
709		- stream = SNDRV_PCM_STREAM_LAST - substream->stream;
710		- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
711		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
712		- I2S_DMACR_TDE_ENABLE,
713		- I2S_DMACR_TDE_ENABLE);
714		- else
715		- regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
716		- I2S_DMACR_RDE_ENABLE,
717		- I2S_DMACR_RDE_ENABLE);
718		-
719		- rockchip_snd_xfer_reset_assert(i2s_tdm);
720		- regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
721		- I2S_XFER_TXS_START \|
722		- I2S_XFER_RXS_START,
723		- I2S_XFER_TXS_START \|
724		- I2S_XFER_RXS_START);
725		- rockchip_snd_xfer_reset_deassert(i2s_tdm);
726		-}
727		-
728	1192	static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
729	1193	struct clk *clk, unsigned long rate,
730	1194	int ppm)
..	..	@@ -840,6 +1304,41 @@
840	1304	return ret;
841	1305	}
842	1306
	1307	+static int rockchip_i2s_tdm_mclk_reparent(struct rk_i2s_tdm_dev *i2s_tdm)
	1308	+{
	1309	+ struct clk *parent;
	1310	+ int ret = 0;
	1311	+
	1312	+ /* reparent to the same clk on TRCM mode */
	1313	+ switch (i2s_tdm->clk_trcm) {
	1314	+ case I2S_CKR_TRCM_TXONLY:
	1315	+ parent = clk_get_parent(i2s_tdm->mclk_tx);
	1316	+ /*
	1317	+ * API clk_has_parent is not available yet on GKI, so we
	1318	+ * use clk_set_parent directly and ignore the ret value.
	1319	+ * if the API has addressed on GKI, should remove it.
	1320	+ */
	1321	+#ifdef CONFIG_NO_GKI
	1322	+ if (clk_has_parent(i2s_tdm->mclk_rx, parent))
	1323	+ ret = clk_set_parent(i2s_tdm->mclk_rx, parent);
	1324	+#else
	1325	+ clk_set_parent(i2s_tdm->mclk_rx, parent);
	1326	+#endif
	1327	+ break;
	1328	+ case I2S_CKR_TRCM_RXONLY:
	1329	+ parent = clk_get_parent(i2s_tdm->mclk_rx);
	1330	+#ifdef CONFIG_NO_GKI
	1331	+ if (clk_has_parent(i2s_tdm->mclk_tx, parent))
	1332	+ ret = clk_set_parent(i2s_tdm->mclk_tx, parent);
	1333	+#else
	1334	+ clk_set_parent(i2s_tdm->mclk_tx, parent);
	1335	+#endif
	1336	+ break;
	1337	+ }
	1338	+
	1339	+ return ret;
	1340	+}
	1341	+
843	1342	static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
844	1343	struct snd_pcm_substream *substream,
845	1344	struct clk **mclk)
..	..	@@ -862,6 +1361,10 @@
862	1361	goto err;
863	1362
864	1363	ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
	1364	+ if (ret)
	1365	+ goto err;
	1366	+
	1367	+ ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
865	1368	if (ret)
866	1369	goto err;
867	1370
..	..	@@ -895,6 +1398,9 @@
895	1398	unsigned int val = 0;
896	1399
897	1400	if (!i2s_tdm->io_multiplex)
	1401	+ return 0;
	1402	+
	1403	+ if (IS_ERR(i2s_tdm->grf))
898	1404	return 0;
899	1405
900	1406	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
..	..	@@ -1006,24 +1512,18 @@
1006	1512	return false;
1007	1513	}
1008	1514
1009		-static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
1010		- struct snd_soc_dai *dai,
1011		- unsigned int div_bclk,
1012		- unsigned int div_lrck,
1013		- unsigned int fmt)
	1515	+static int rockchip_i2s_tdm_params_trcm(struct snd_pcm_substream *substream,
	1516	+ struct snd_soc_dai *dai,
	1517	+ unsigned int div_bclk,
	1518	+ unsigned int div_lrck,
	1519	+ unsigned int fmt)
1014	1520	{
1015	1521	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1016	1522	unsigned long flags;
1017	1523
1018		- if (!i2s_tdm->clk_trcm)
1019		- return 0;
1020		-
1021		- if (!is_params_dirty(substream, dai, div_bclk, div_lrck, fmt))
1022		- return 0;
1023		-
1024	1524	spin_lock_irqsave(&i2s_tdm->lock, flags);
1025	1525	if (atomic_read(&i2s_tdm->refcount))
1026		- rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
	1526	+ rockchip_i2s_tdm_trcm_pause(substream, i2s_tdm);
1027	1527
1028	1528	regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1029	1529	I2S_CLKDIV_TXM_MASK \| I2S_CLKDIV_RXM_MASK,
..	..	@@ -1042,8 +1542,56 @@
1042	1542	fmt);
1043	1543
1044	1544	if (atomic_read(&i2s_tdm->refcount))
1045		- rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
	1545	+ rockchip_i2s_tdm_trcm_resume(substream, i2s_tdm);
1046	1546	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
	1547	+
	1548	+ return 0;
	1549	+}
	1550	+
	1551	+static int rockchip_i2s_tdm_params(struct snd_pcm_substream *substream,
	1552	+ struct snd_soc_dai *dai,
	1553	+ unsigned int div_bclk,
	1554	+ unsigned int div_lrck,
	1555	+ unsigned int fmt)
	1556	+{
	1557	+ struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
	1558	+ int stream = substream->stream;
	1559	+
	1560	+ if (is_stream_active(i2s_tdm, stream))
	1561	+ rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
	1562	+
	1563	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
	1564	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
	1565	+ I2S_CLKDIV_TXM_MASK,
	1566	+ I2S_CLKDIV_TXM(div_bclk));
	1567	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	1568	+ I2S_CKR_TSD_MASK,
	1569	+ I2S_CKR_TSD(div_lrck));
	1570	+ regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
	1571	+ I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
	1572	+ fmt);
	1573	+ } else {
	1574	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
	1575	+ I2S_CLKDIV_RXM_MASK,
	1576	+ I2S_CLKDIV_RXM(div_bclk));
	1577	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	1578	+ I2S_CKR_RSD_MASK,
	1579	+ I2S_CKR_RSD(div_lrck));
	1580	+ regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
	1581	+ I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
	1582	+ fmt);
	1583	+ }
	1584	+
	1585	+ /*
	1586	+ * Bring back CLK ASAP after cfg changed to make SINK devices active
	1587	+ * on HDMI-PATH-ALWAYS-ON situation, this workaround for some TVs no
	1588	+ * sound issue. at the moment, it's 8K@60Hz display situation.
	1589	+ */
	1590	+ if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
	1591	+ (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
	1592	+ (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) {
	1593	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
	1594	+ }
1047	1595
1048	1596	return 0;
1049	1597	}
..	..	@@ -1056,6 +1604,32 @@
1056	1604	unsigned int reg_fmt, fmt;
1057	1605	int ret = 0;
1058	1606
	1607	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	1608	+ if (i2s_tdm->is_tdm_multi_lanes) {
	1609	+ unsigned int lanes = rockchip_i2s_tdm_get_lanes(i2s_tdm,
	1610	+ substream->stream);
	1611	+
	1612	+ switch (lanes) {
	1613	+ case 4:
	1614	+ ret = I2S_CHN_8;
	1615	+ break;
	1616	+ case 3:
	1617	+ ret = I2S_CHN_6;
	1618	+ break;
	1619	+ case 2:
	1620	+ ret = I2S_CHN_4;
	1621	+ break;
	1622	+ case 1:
	1623	+ ret = I2S_CHN_2;
	1624	+ break;
	1625	+ default:
	1626	+ ret = -EINVAL;
	1627	+ break;
	1628	+ }
	1629	+
	1630	+ return ret;
	1631	+ }
	1632	+#endif
1059	1633	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1060	1634	reg_fmt = I2S_TXCR;
1061	1635	else
..	..	@@ -1105,34 +1679,60 @@
1105	1679	return ret;
1106	1680	}
1107	1681
	1682	+static void rockchip_i2s_tdm_get_performance(struct snd_pcm_substream *substream,
	1683	+ struct snd_pcm_hw_params *params,
	1684	+ struct snd_soc_dai *dai,
	1685	+ unsigned int csr)
	1686	+{
	1687	+ struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
	1688	+ unsigned int tdl;
	1689	+ int fifo;
	1690	+
	1691	+ regmap_read(i2s_tdm->regmap, I2S_DMACR, &tdl);
	1692	+
	1693	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	1694	+ fifo = I2S_DMACR_TDL_V(tdl) * I2S_TXCR_CSR_V(csr);
	1695	+ else
	1696	+ fifo = I2S_DMACR_RDL_V(tdl) * I2S_RXCR_CSR_V(csr);
	1697	+
	1698	+ rockchip_utils_get_performance(substream, params, dai, fifo);
	1699	+}
	1700	+
1108	1701	static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
1109	1702	struct snd_pcm_hw_params *params,
1110	1703	struct snd_soc_dai *dai)
1111	1704	{
1112	1705	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
	1706	+ struct snd_dmaengine_dai_dma_data *dma_data;
1113	1707	struct clk *mclk;
1114	1708	int ret = 0;
1115	1709	unsigned int val = 0;
1116		- unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
	1710	+ unsigned int mclk_rate, bclk_rate, lrck_rate, div_bclk = 4, div_lrck = 64;
1117	1711
1118		- if (i2s_tdm->is_master_mode) {
1119		- if (i2s_tdm->mclk_calibrate)
1120		- rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
1121		- params_rate(params));
	1712	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	1713	+ if (i2s_tdm->is_tdm_multi_lanes)
	1714	+ rockchip_i2s_tdm_multi_lanes_set_clk(substream, params, dai);
	1715	+#endif
	1716	+ dma_data = snd_soc_dai_get_dma_data(dai, substream);
	1717	+ dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
1122	1718
1123		- ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
1124		- if (ret)
1125		- goto err;
	1719	+ if (i2s_tdm->mclk_calibrate)
	1720	+ rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
	1721	+ params_rate(params));
1126	1722
1127		- mclk_rate = clk_get_rate(mclk);
1128		- bclk_rate = i2s_tdm->bclk_fs * params_rate(params);
1129		- if (!bclk_rate) {
1130		- ret = -EINVAL;
1131		- goto err;
1132		- }
1133		- div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
1134		- div_lrck = bclk_rate / params_rate(params);
	1723	+ ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
	1724	+ if (ret)
	1725	+ goto err;
	1726	+
	1727	+ mclk_rate = clk_get_rate(mclk);
	1728	+ lrck_rate = params_rate(params) * i2s_tdm->lrck_ratio;
	1729	+ bclk_rate = i2s_tdm->bclk_fs * lrck_rate;
	1730	+ if (!bclk_rate) {
	1731	+ ret = -EINVAL;
	1732	+ goto err;
1135	1733	}
	1734	+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
	1735	+ div_lrck = bclk_rate / lrck_rate;
1136	1736
1137	1737	switch (params_format(params)) {
1138	1738	case SNDRV_PCM_FORMAT_S8:
..	..	@@ -1148,6 +1748,7 @@
1148	1748	val \|= I2S_TXCR_VDW(24);
1149	1749	break;
1150	1750	case SNDRV_PCM_FORMAT_S32_LE:
	1751	+ case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
1151	1752	val \|= I2S_TXCR_VDW(32);
1152	1753	break;
1153	1754	default:
..	..	@@ -1159,35 +1760,28 @@
1159	1760	if (ret < 0)
1160	1761	goto err;
1161	1762
	1763	+ rockchip_i2s_tdm_get_performance(substream, params, dai, ret);
	1764	+
1162	1765	val \|= ret;
1163		- if (i2s_tdm->clk_trcm) {
1164		- rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
1165		- } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1166		- regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1167		- I2S_CLKDIV_TXM_MASK,
1168		- I2S_CLKDIV_TXM(div_bclk));
1169		- regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1170		- I2S_CKR_TSD_MASK,
1171		- I2S_CKR_TSD(div_lrck));
1172		- regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1173		- I2S_TXCR_VDW_MASK \| I2S_TXCR_CSR_MASK,
1174		- val);
1175		- } else {
1176		- regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1177		- I2S_CLKDIV_RXM_MASK,
1178		- I2S_CLKDIV_RXM(div_bclk));
1179		- regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1180		- I2S_CKR_RSD_MASK,
1181		- I2S_CKR_RSD(div_lrck));
1182		- regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1183		- I2S_RXCR_VDW_MASK \| I2S_RXCR_CSR_MASK,
1184		- val);
1185		- }
	1766	+ if (!is_params_dirty(substream, dai, div_bclk, div_lrck, val))
	1767	+ return 0;
	1768	+
	1769	+ if (i2s_tdm->clk_trcm)
	1770	+ rockchip_i2s_tdm_params_trcm(substream, dai, div_bclk, div_lrck, val);
	1771	+ else
	1772	+ rockchip_i2s_tdm_params(substream, dai, div_bclk, div_lrck, val);
1186	1773
1187	1774	ret = rockchip_i2s_io_multiplex(substream, dai);
1188	1775
1189	1776	err:
1190	1777	return ret;
	1778	+}
	1779	+static int rockchip_i2s_tdm_hw_free(struct snd_pcm_substream *substream,
	1780	+ struct snd_soc_dai *dai)
	1781	+{
	1782	+ rockchip_utils_put_performance(substream, dai);
	1783	+
	1784	+ return 0;
1191	1785	}
1192	1786
1193	1787	static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
..	..	@@ -1200,22 +1794,12 @@
1200	1794	case SNDRV_PCM_TRIGGER_START:
1201	1795	case SNDRV_PCM_TRIGGER_RESUME:
1202	1796	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1203		- if (i2s_tdm->clk_trcm)
1204		- rockchip_snd_txrxctrl(substream, dai, 1);
1205		- else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1206		- rockchip_snd_rxctrl(i2s_tdm, 1);
1207		- else
1208		- rockchip_snd_txctrl(i2s_tdm, 1);
	1797	+ rockchip_i2s_tdm_start(i2s_tdm, substream->stream);
1209	1798	break;
1210	1799	case SNDRV_PCM_TRIGGER_SUSPEND:
1211	1800	case SNDRV_PCM_TRIGGER_STOP:
1212	1801	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1213		- if (i2s_tdm->clk_trcm)
1214		- rockchip_snd_txrxctrl(substream, dai, 0);
1215		- else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1216		- rockchip_snd_rxctrl(i2s_tdm, 0);
1217		- else
1218		- rockchip_snd_txctrl(i2s_tdm, 0);
	1802	+ rockchip_i2s_tdm_stop(i2s_tdm, substream->stream);
1219	1803	break;
1220	1804	default:
1221	1805	ret = -EINVAL;
..	..	@@ -1262,8 +1846,8 @@
1262	1846	static int rockchip_i2s_tdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
1263	1847	struct snd_ctl_elem_value *ucontrol)
1264	1848	{
1265		- struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1266		- struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
	1849	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1850	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
1267	1851
1268	1852	ucontrol->value.integer.value[0] = i2s_tdm->clk_ppm;
1269	1853
..	..	@@ -1273,8 +1857,8 @@
1273	1857	static int rockchip_i2s_tdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
1274	1858	struct snd_ctl_elem_value *ucontrol)
1275	1859	{
1276		- struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
1277		- struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
	1860	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1861	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
1278	1862	int ret = 0, ppm = 0;
1279	1863
1280	1864	if ((ucontrol->value.integer.value[0] < CLK_PPM_MIN) \|\|
..	..	@@ -1305,6 +1889,199 @@
1305	1889	.put = rockchip_i2s_tdm_clk_compensation_put,
1306	1890	};
1307	1891
	1892	+/* loopback mode select */
	1893	+enum {
	1894	+ LOOPBACK_MODE_DIS = 0,
	1895	+ LOOPBACK_MODE_1,
	1896	+ LOOPBACK_MODE_2,
	1897	+ LOOPBACK_MODE_2_SWAP,
	1898	+};
	1899	+
	1900	+static const char *const loopback_text[] = {
	1901	+ "Disabled",
	1902	+ "Mode1",
	1903	+ "Mode2",
	1904	+ "Mode2 Swap",
	1905	+};
	1906	+
	1907	+static SOC_ENUM_SINGLE_EXT_DECL(loopback_mode, loopback_text);
	1908	+
	1909	+static int rockchip_i2s_tdm_loopback_get(struct snd_kcontrol *kcontrol,
	1910	+ struct snd_ctl_elem_value *ucontrol)
	1911	+{
	1912	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1913	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	1914	+ unsigned int reg = 0, mode = 0;
	1915	+
	1916	+ pm_runtime_get_sync(component->dev);
	1917	+ regmap_read(i2s_tdm->regmap, I2S_XFER, &reg);
	1918	+ pm_runtime_put(component->dev);
	1919	+
	1920	+ switch (reg & I2S_XFER_LP_MODE_MASK) {
	1921	+ case I2S_XFER_LP_MODE_2_SWAP:
	1922	+ mode = LOOPBACK_MODE_2_SWAP;
	1923	+ break;
	1924	+ case I2S_XFER_LP_MODE_2:
	1925	+ mode = LOOPBACK_MODE_2;
	1926	+ break;
	1927	+ case I2S_XFER_LP_MODE_1:
	1928	+ mode = LOOPBACK_MODE_1;
	1929	+ break;
	1930	+ default:
	1931	+ mode = LOOPBACK_MODE_DIS;
	1932	+ break;
	1933	+ }
	1934	+
	1935	+ ucontrol->value.enumerated.item[0] = mode;
	1936	+
	1937	+ return 0;
	1938	+}
	1939	+
	1940	+static int rockchip_i2s_tdm_loopback_put(struct snd_kcontrol *kcontrol,
	1941	+ struct snd_ctl_elem_value *ucontrol)
	1942	+{
	1943	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1944	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	1945	+ unsigned int val = 0, mode = ucontrol->value.enumerated.item[0];
	1946	+
	1947	+ if (mode < LOOPBACK_MODE_DIS \|\|
	1948	+ mode > LOOPBACK_MODE_2_SWAP)
	1949	+ return -EINVAL;
	1950	+
	1951	+ switch (mode) {
	1952	+ case LOOPBACK_MODE_2_SWAP:
	1953	+ val = I2S_XFER_LP_MODE_2_SWAP;
	1954	+ break;
	1955	+ case LOOPBACK_MODE_2:
	1956	+ val = I2S_XFER_LP_MODE_2;
	1957	+ break;
	1958	+ case LOOPBACK_MODE_1:
	1959	+ val = I2S_XFER_LP_MODE_1;
	1960	+ break;
	1961	+ default:
	1962	+ val = I2S_XFER_LP_MODE_DIS;
	1963	+ break;
	1964	+ }
	1965	+
	1966	+ pm_runtime_get_sync(component->dev);
	1967	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER, I2S_XFER_LP_MODE_MASK, val);
	1968	+ pm_runtime_put(component->dev);
	1969	+
	1970	+ return 0;
	1971	+}
	1972	+
	1973	+static const char * const rpaths_text[] = {
	1974	+ "From SDI0", "From SDI1", "From SDI2", "From SDI3" };
	1975	+
	1976	+static const char * const tpaths_text[] = {
	1977	+ "From PATH0", "From PATH1", "From PATH2", "From PATH3" };
	1978	+
	1979	+/* TXCR */
	1980	+static SOC_ENUM_SINGLE_DECL(tpath3_enum, I2S_TXCR, 29, tpaths_text);
	1981	+static SOC_ENUM_SINGLE_DECL(tpath2_enum, I2S_TXCR, 27, tpaths_text);
	1982	+static SOC_ENUM_SINGLE_DECL(tpath1_enum, I2S_TXCR, 25, tpaths_text);
	1983	+static SOC_ENUM_SINGLE_DECL(tpath0_enum, I2S_TXCR, 23, tpaths_text);
	1984	+
	1985	+/* RXCR */
	1986	+static SOC_ENUM_SINGLE_DECL(rpath3_enum, I2S_RXCR, 23, rpaths_text);
	1987	+static SOC_ENUM_SINGLE_DECL(rpath2_enum, I2S_RXCR, 21, rpaths_text);
	1988	+static SOC_ENUM_SINGLE_DECL(rpath1_enum, I2S_RXCR, 19, rpaths_text);
	1989	+static SOC_ENUM_SINGLE_DECL(rpath0_enum, I2S_RXCR, 17, rpaths_text);
	1990	+
	1991	+static int rockchip_i2s_tdm_wait_time_info(struct snd_kcontrol *kcontrol,
	1992	+ struct snd_ctl_elem_info *uinfo)
	1993	+{
	1994	+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	1995	+ uinfo->count = 1;
	1996	+ uinfo->value.integer.min = 0;
	1997	+ uinfo->value.integer.max = WAIT_TIME_MS_MAX;
	1998	+ uinfo->value.integer.step = 1;
	1999	+
	2000	+ return 0;
	2001	+}
	2002	+
	2003	+static int rockchip_i2s_tdm_rd_wait_time_get(struct snd_kcontrol *kcontrol,
	2004	+ struct snd_ctl_elem_value *ucontrol)
	2005	+{
	2006	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	2007	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	2008	+
	2009	+ ucontrol->value.integer.value[0] = i2s_tdm->wait_time[SNDRV_PCM_STREAM_CAPTURE];
	2010	+
	2011	+ return 0;
	2012	+}
	2013	+
	2014	+static int rockchip_i2s_tdm_rd_wait_time_put(struct snd_kcontrol *kcontrol,
	2015	+ struct snd_ctl_elem_value *ucontrol)
	2016	+{
	2017	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	2018	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	2019	+
	2020	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	2021	+ return -EINVAL;
	2022	+
	2023	+ i2s_tdm->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
	2024	+
	2025	+ return 1;
	2026	+}
	2027	+
	2028	+static int rockchip_i2s_tdm_wr_wait_time_get(struct snd_kcontrol *kcontrol,
	2029	+ struct snd_ctl_elem_value *ucontrol)
	2030	+{
	2031	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	2032	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	2033	+
	2034	+ ucontrol->value.integer.value[0] = i2s_tdm->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
	2035	+
	2036	+ return 0;
	2037	+}
	2038	+
	2039	+static int rockchip_i2s_tdm_wr_wait_time_put(struct snd_kcontrol *kcontrol,
	2040	+ struct snd_ctl_elem_value *ucontrol)
	2041	+{
	2042	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	2043	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	2044	+
	2045	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	2046	+ return -EINVAL;
	2047	+
	2048	+ i2s_tdm->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
	2049	+
	2050	+ return 1;
	2051	+}
	2052	+
	2053	+#define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \
	2054	+{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \
	2055	+ .info = rockchip_i2s_tdm_wait_time_info, \
	2056	+ .get = xhandler_get, .put = xhandler_put }
	2057	+
	2058	+static const struct snd_kcontrol_new rockchip_i2s_tdm_snd_controls[] = {
	2059	+ SOC_ENUM("Receive PATH3 Source Select", rpath3_enum),
	2060	+ SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
	2061	+ SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
	2062	+ SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
	2063	+ SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
	2064	+ SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
	2065	+ SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
	2066	+ SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
	2067	+
	2068	+ SOC_ENUM_EXT("I2STDM Digital Loopback Mode", loopback_mode,
	2069	+ rockchip_i2s_tdm_loopback_get,
	2070	+ rockchip_i2s_tdm_loopback_put),
	2071	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	2072	+ SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
	2073	+ rockchip_i2s_tdm_tx_lanes_get, rockchip_i2s_tdm_tx_lanes_put),
	2074	+ SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
	2075	+ rockchip_i2s_tdm_rx_lanes_get, rockchip_i2s_tdm_rx_lanes_put),
	2076	+#endif
	2077	+ SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
	2078	+ rockchip_i2s_tdm_rd_wait_time_get,
	2079	+ rockchip_i2s_tdm_rd_wait_time_put),
	2080	+ SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
	2081	+ rockchip_i2s_tdm_wr_wait_time_get,
	2082	+ rockchip_i2s_tdm_wr_wait_time_put),
	2083	+};
	2084	+
1308	2085	static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1309	2086	{
1310	2087	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
..	..	@@ -1313,7 +2090,9 @@
1313	2090	dai->playback_dma_data = &i2s_tdm->playback_dma_data;
1314	2091
1315	2092	if (i2s_tdm->mclk_calibrate)
1316		- snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
	2093	+ snd_soc_add_component_controls(dai->component,
	2094	+ &rockchip_i2s_tdm_compensation_control,
	2095	+ 1);
1317	2096
1318	2097	return 0;
1319	2098	}
..	..	@@ -1340,8 +2119,36 @@
1340	2119	return 0;
1341	2120	}
1342	2121
	2122	+static int rockchip_i2s_tdm_startup(struct snd_pcm_substream *substream,
	2123	+ struct snd_soc_dai *dai)
	2124	+{
	2125	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
	2126	+ int stream = substream->stream;
	2127	+
	2128	+ if (i2s_tdm->substreams[stream])
	2129	+ return -EBUSY;
	2130	+
	2131	+ if (i2s_tdm->wait_time[stream])
	2132	+ substream->wait_time = msecs_to_jiffies(i2s_tdm->wait_time[stream]);
	2133	+
	2134	+ i2s_tdm->substreams[stream] = substream;
	2135	+
	2136	+ return 0;
	2137	+}
	2138	+
	2139	+static void rockchip_i2s_tdm_shutdown(struct snd_pcm_substream *substream,
	2140	+ struct snd_soc_dai *dai)
	2141	+{
	2142	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
	2143	+
	2144	+ i2s_tdm->substreams[substream->stream] = NULL;
	2145	+}
	2146	+
1343	2147	static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
	2148	+ .startup = rockchip_i2s_tdm_startup,
	2149	+ .shutdown = rockchip_i2s_tdm_shutdown,
1344	2150	.hw_params = rockchip_i2s_tdm_hw_params,
	2151	+ .hw_free = rockchip_i2s_tdm_hw_free,
1345	2152	.set_sysclk = rockchip_i2s_tdm_set_sysclk,
1346	2153	.set_fmt = rockchip_i2s_tdm_set_fmt,
1347	2154	.set_tdm_slot = rockchip_dai_tdm_slot,
..	..	@@ -1350,6 +2157,8 @@
1350	2157
1351	2158	static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1352	2159	.name = DRV_NAME,
	2160	+ .controls = rockchip_i2s_tdm_snd_controls,
	2161	+ .num_controls = ARRAY_SIZE(rockchip_i2s_tdm_snd_controls),
1353	2162	};
1354	2163
1355	2164	static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
..	..	@@ -1400,6 +2209,7 @@
1400	2209	{
1401	2210	switch (reg) {
1402	2211	case I2S_TXFIFOLR:
	2212	+ case I2S_INTCR:
1403	2213	case I2S_INTSR:
1404	2214	case I2S_CLR:
1405	2215	case I2S_TXDR:
..	..	@@ -1453,9 +2263,11 @@
1453	2263	u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1454	2264	int i;
1455	2265
	2266	+ if (IS_ERR(i2s_tdm->grf))
	2267	+ return 0;
	2268	+
1456	2269	switch (trcm) {
1457	2270	case I2S_CKR_TRCM_TXONLY:
1458		- /* fall through */
1459	2271	case I2S_CKR_TRCM_RXONLY:
1460	2272	break;
1461	2273	default:
..	..	@@ -1551,6 +2363,12 @@
1551	2363	#ifdef CONFIG_CPU_RK3568
1552	2364	{ .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1553	2365	#endif
	2366	+#ifdef CONFIG_CPU_RK3588
	2367	+ { .compatible = "rockchip,rk3588-i2s-tdm", },
	2368	+#endif
	2369	+#ifdef CONFIG_CPU_RV1106
	2370	+ { .compatible = "rockchip,rv1106-i2s-tdm", },
	2371	+#endif
1554	2372	#ifdef CONFIG_CPU_RV1126
1555	2373	{ .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1556	2374	#endif
..	..	@@ -1585,24 +2403,26 @@
1585	2403	.playback = {
1586	2404	.stream_name = "Playback",
1587	2405	.channels_min = 2,
1588		- .channels_max = 16,
	2406	+ .channels_max = 64,
1589	2407	.rates = SNDRV_PCM_RATE_8000_192000,
1590	2408	.formats = (SNDRV_PCM_FMTBIT_S8 \|
1591	2409	SNDRV_PCM_FMTBIT_S16_LE \|
1592	2410	SNDRV_PCM_FMTBIT_S20_3LE \|
1593	2411	SNDRV_PCM_FMTBIT_S24_LE \|
1594		- SNDRV_PCM_FMTBIT_S32_LE),
	2412	+ SNDRV_PCM_FMTBIT_S32_LE \|
	2413	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
1595	2414	},
1596	2415	.capture = {
1597	2416	.stream_name = "Capture",
1598	2417	.channels_min = 2,
1599		- .channels_max = 16,
	2418	+ .channels_max = 64,
1600	2419	.rates = SNDRV_PCM_RATE_8000_192000,
1601	2420	.formats = (SNDRV_PCM_FMTBIT_S8 \|
1602	2421	SNDRV_PCM_FMTBIT_S16_LE \|
1603	2422	SNDRV_PCM_FMTBIT_S20_3LE \|
1604	2423	SNDRV_PCM_FMTBIT_S24_LE \|
1605		- SNDRV_PCM_FMTBIT_S32_LE),
	2424	+ SNDRV_PCM_FMTBIT_S32_LE \|
	2425	+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
1606	2426	},
1607	2427	.ops = &rockchip_i2s_tdm_dai_ops,
1608	2428	};
..	..	@@ -1758,6 +2578,124 @@
1758	2578	return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1759	2579	}
1760	2580
	2581	+static int rockchip_i2s_tdm_get_fifo_count(struct device *dev,
	2582	+ struct snd_pcm_substream *substream)
	2583	+{
	2584	+ struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
	2585	+ int val = 0;
	2586	+
	2587	+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
	2588	+ regmap_read(i2s_tdm->regmap, I2S_TXFIFOLR, &val);
	2589	+ else
	2590	+ regmap_read(i2s_tdm->regmap, I2S_RXFIFOLR, &val);
	2591	+
	2592	+ val = ((val & I2S_FIFOLR_TFL3_MASK) >> I2S_FIFOLR_TFL3_SHIFT) +
	2593	+ ((val & I2S_FIFOLR_TFL2_MASK) >> I2S_FIFOLR_TFL2_SHIFT) +
	2594	+ ((val & I2S_FIFOLR_TFL1_MASK) >> I2S_FIFOLR_TFL1_SHIFT) +
	2595	+ ((val & I2S_FIFOLR_TFL0_MASK) >> I2S_FIFOLR_TFL0_SHIFT);
	2596	+
	2597	+ return val;
	2598	+}
	2599	+
	2600	+static const struct snd_dlp_config dconfig = {
	2601	+ .get_fifo_count = rockchip_i2s_tdm_get_fifo_count,
	2602	+};
	2603	+
	2604	+static irqreturn_t rockchip_i2s_tdm_isr(int irq, void *devid)
	2605	+{
	2606	+ struct rk_i2s_tdm_dev i2s_tdm = (struct rk_i2s_tdm_dev )devid;
	2607	+ struct snd_pcm_substream *substream;
	2608	+ u32 val;
	2609	+
	2610	+ regmap_read(i2s_tdm->regmap, I2S_INTSR, &val);
	2611	+ if (val & I2S_INTSR_TXUI_ACT) {
	2612	+ dev_warn_ratelimited(i2s_tdm->dev, "TX FIFO Underrun\n");
	2613	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2614	+ I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
	2615	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2616	+ I2S_INTCR_TXUIE_MASK,
	2617	+ I2S_INTCR_TXUIE(0));
	2618	+ substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_PLAYBACK];
	2619	+ if (substream)
	2620	+ snd_pcm_stop_xrun(substream);
	2621	+ }
	2622	+
	2623	+ if (val & I2S_INTSR_RXOI_ACT) {
	2624	+ dev_warn_ratelimited(i2s_tdm->dev, "RX FIFO Overrun\n");
	2625	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2626	+ I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
	2627	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2628	+ I2S_INTCR_RXOIE_MASK,
	2629	+ I2S_INTCR_RXOIE(0));
	2630	+ substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_CAPTURE];
	2631	+ if (substream)
	2632	+ snd_pcm_stop_xrun(substream);
	2633	+ }
	2634	+
	2635	+ return IRQ_HANDLED;
	2636	+}
	2637	+
	2638	+static int rockchip_i2s_tdm_keep_clk_always_on(struct rk_i2s_tdm_dev *i2s_tdm)
	2639	+{
	2640	+ unsigned int mclk_rate = DEFAULT_FS * DEFAULT_MCLK_FS;
	2641	+ unsigned int bclk_rate = i2s_tdm->bclk_fs * DEFAULT_FS;
	2642	+ unsigned int div_lrck = i2s_tdm->bclk_fs;
	2643	+ unsigned int div_bclk;
	2644	+ int ret;
	2645	+
	2646	+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
	2647	+
	2648	+ /* assign generic freq */
	2649	+ clk_set_rate(i2s_tdm->mclk_rx, mclk_rate);
	2650	+ clk_set_rate(i2s_tdm->mclk_tx, mclk_rate);
	2651	+
	2652	+ ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
	2653	+ if (ret)
	2654	+ return ret;
	2655	+
	2656	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
	2657	+ I2S_CLKDIV_RXM_MASK \| I2S_CLKDIV_TXM_MASK,
	2658	+ I2S_CLKDIV_RXM(div_bclk) \| I2S_CLKDIV_TXM(div_bclk));
	2659	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	2660	+ I2S_CKR_RSD_MASK \| I2S_CKR_TSD_MASK,
	2661	+ I2S_CKR_RSD(div_lrck) \| I2S_CKR_TSD(div_lrck));
	2662	+
	2663	+ if (i2s_tdm->clk_trcm)
	2664	+ rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
	2665	+ else
	2666	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
	2667	+
	2668	+ pm_runtime_forbid(i2s_tdm->dev);
	2669	+
	2670	+ dev_info(i2s_tdm->dev, "CLK-ALWAYS-ON: mclk: %d, bclk: %d, fsync: %d\n",
	2671	+ mclk_rate, bclk_rate, DEFAULT_FS);
	2672	+
	2673	+ return 0;
	2674	+}
	2675	+
	2676	+static int rockchip_i2s_tdm_register_platform(struct device *dev)
	2677	+{
	2678	+ int ret = 0;
	2679	+
	2680	+ if (device_property_read_bool(dev, "rockchip,no-dmaengine")) {
	2681	+ dev_info(dev, "Used for Multi-DAI\n");
	2682	+ return 0;
	2683	+ }
	2684	+
	2685	+ if (device_property_read_bool(dev, "rockchip,digital-loopback")) {
	2686	+ ret = devm_snd_dmaengine_dlp_register(dev, &dconfig);
	2687	+ if (ret)
	2688	+ dev_err(dev, "Could not register DLP\n");
	2689	+ return ret;
	2690	+ }
	2691	+
	2692	+ ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
	2693	+ if (ret)
	2694	+ dev_err(dev, "Could not register PCM\n");
	2695	+
	2696	+ return ret;
	2697	+}
	2698	+
1761	2699	static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1762	2700	{
1763	2701	struct device_node *node = pdev->dev.of_node;
..	..	@@ -1769,8 +2707,7 @@
1769	2707	#ifdef HAVE_SYNC_RESET
1770	2708	bool sync;
1771	2709	#endif
1772		- int ret;
1773		- int val;
	2710	+ int ret, val, i, irq;
1774	2711
1775	2712	ret = rockchip_i2s_tdm_dai_prepare(pdev, &soc_dai);
1776	2713	if (ret)
..	..	@@ -1781,13 +2718,70 @@
1781	2718	return -ENOMEM;
1782	2719
1783	2720	i2s_tdm->dev = &pdev->dev;
	2721	+ i2s_tdm->lrck_ratio = 1;
1784	2722
1785	2723	of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
1786		- if (!of_id \|\| !of_id->data)
	2724	+ if (!of_id)
1787	2725	return -EINVAL;
	2726	+
	2727	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	2728	+ i2s_tdm->is_tdm_multi_lanes =
	2729	+ device_property_read_bool(i2s_tdm->dev, "rockchip,tdm-multi-lanes");
	2730	+
	2731	+ if (i2s_tdm->is_tdm_multi_lanes) {
	2732	+ struct device_node *clk_src_node = NULL;
	2733	+
	2734	+ i2s_tdm->tx_lanes = 1;
	2735	+ i2s_tdm->rx_lanes = 1;
	2736	+
	2737	+ if (!device_property_read_u32(i2s_tdm->dev, "rockchip,tdm-tx-lanes", &val)) {
	2738	+ if ((val >= 1) && (val <= 4))
	2739	+ i2s_tdm->tx_lanes = val;
	2740	+ }
	2741	+
	2742	+ if (!device_property_read_u32(i2s_tdm->dev, "rockchip,tdm-rx-lanes", &val)) {
	2743	+ if ((val >= 1) && (val <= 4))
	2744	+ i2s_tdm->rx_lanes = val;
	2745	+ }
	2746	+
	2747	+ i2s_tdm->i2s_lrck_gpio = devm_gpiod_get_optional(&pdev->dev, "i2s-lrck", GPIOD_IN);
	2748	+ if (IS_ERR(i2s_tdm->i2s_lrck_gpio)) {
	2749	+ ret = PTR_ERR(i2s_tdm->i2s_lrck_gpio);
	2750	+ dev_err(&pdev->dev, "Failed to get i2s_lrck_gpio %d\n", ret);
	2751	+ return ret;
	2752	+ }
	2753	+
	2754	+ i2s_tdm->tdm_fsync_gpio = devm_gpiod_get_optional(&pdev->dev, "tdm-fsync", GPIOD_IN);
	2755	+ if (IS_ERR(i2s_tdm->tdm_fsync_gpio)) {
	2756	+ ret = PTR_ERR(i2s_tdm->tdm_fsync_gpio);
	2757	+ dev_err(&pdev->dev, "Failed to get tdm_fsync_gpio %d\n", ret);
	2758	+ return ret;
	2759	+ }
	2760	+
	2761	+ /* It's optional, required when use soc clk src, such as: i2s2_2ch */
	2762	+ clk_src_node = of_parse_phandle(node, "rockchip,clk-src", 0);
	2763	+ if (clk_src_node) {
	2764	+ i2s_tdm->clk_src_base = of_iomap(clk_src_node, 0);
	2765	+ if (!i2s_tdm->clk_src_base)
	2766	+ return -ENOENT;
	2767	+
	2768	+ i2s_tdm->clk_src_dai = rockchip_i2s_tdm_find_dai(clk_src_node);
	2769	+ if (!i2s_tdm->clk_src_dai)
	2770	+ return -EPROBE_DEFER;
	2771	+
	2772	+ pm_runtime_forbid(i2s_tdm->clk_src_dai->dev);
	2773	+ }
	2774	+
	2775	+ dev_info(&pdev->dev, "Used as TDM_MULTI_LANES mode\n");
	2776	+ }
	2777	+#endif
1788	2778
1789	2779	spin_lock_init(&i2s_tdm->lock);
1790	2780	i2s_tdm->soc_data = (const struct rk_i2s_soc_data *)of_id->data;
	2781	+
	2782	+ for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
	2783	+ if (of_property_read_bool(node, of_quirks[i].quirk))
	2784	+ i2s_tdm->quirks \|= of_quirks[i].id;
1791	2785
1792	2786	i2s_tdm->bclk_fs = 64;
1793	2787	if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) {
..	..	@@ -1813,8 +2807,15 @@
1813	2807	soc_dai->playback.channels_min = 0;
1814	2808
1815	2809	i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1816		- if (IS_ERR(i2s_tdm->grf))
1817		- return PTR_ERR(i2s_tdm->grf);
	2810	+
	2811	+ i2s_tdm->pinctrl = devm_pinctrl_get(&pdev->dev);
	2812	+ if (!IS_ERR_OR_NULL(i2s_tdm->pinctrl)) {
	2813	+ i2s_tdm->clk_state = pinctrl_lookup_state(i2s_tdm->pinctrl, "clk");
	2814	+ if (IS_ERR(i2s_tdm->clk_state)) {
	2815	+ i2s_tdm->clk_state = NULL;
	2816	+ dev_dbg(i2s_tdm->dev, "Have no clk pinctrl state\n");
	2817	+ }
	2818	+ }
1818	2819
1819	2820	#ifdef HAVE_SYNC_RESET
1820	2821	sync = of_device_is_compatible(node, "rockchip,px30-i2s-tdm") \|\|
..	..	@@ -1892,23 +2893,32 @@
1892	2893	i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1893	2894	}
1894	2895
1895		- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1896		- regs = devm_ioremap_resource(&pdev->dev, res);
	2896	+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1897	2897	if (IS_ERR(regs))
1898	2898	return PTR_ERR(regs);
1899	2899
1900	2900	i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1901		- &rockchip_i2s_tdm_regmap_config);
	2901	+ &rockchip_i2s_tdm_regmap_config);
1902	2902	if (IS_ERR(i2s_tdm->regmap))
1903	2903	return PTR_ERR(i2s_tdm->regmap);
1904	2904
	2905	+ irq = platform_get_irq_optional(pdev, 0);
	2906	+ if (irq > 0) {
	2907	+ ret = devm_request_irq(&pdev->dev, irq, rockchip_i2s_tdm_isr,
	2908	+ IRQF_SHARED, node->name, i2s_tdm);
	2909	+ if (ret) {
	2910	+ dev_err(&pdev->dev, "failed to request irq %u\n", irq);
	2911	+ return ret;
	2912	+ }
	2913	+ }
	2914	+
1905	2915	i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1906	2916	i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1907		- i2s_tdm->playback_dma_data.maxburst = 8;
	2917	+ i2s_tdm->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
1908	2918
1909	2919	i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1910	2920	i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1911		- i2s_tdm->capture_dma_data.maxburst = 8;
	2921	+ i2s_tdm->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
1912	2922
1913	2923	ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1914	2924	if (ret < 0) {
..	..	@@ -1925,13 +2935,6 @@
1925	2935	atomic_set(&i2s_tdm->refcount, 0);
1926	2936	dev_set_drvdata(&pdev->dev, i2s_tdm);
1927	2937
1928		- pm_runtime_enable(&pdev->dev);
1929		- if (!pm_runtime_enabled(&pdev->dev)) {
1930		- ret = i2s_tdm_runtime_resume(&pdev->dev);
1931		- if (ret)
1932		- goto err_pm_disable;
1933		- }
1934		-
1935	2938	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1936	2939	I2S_DMACR_TDL(16));
1937	2940	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
..	..	@@ -1942,21 +2945,44 @@
1942	2945	if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1943	2946	i2s_tdm->soc_data->init(&pdev->dev, res->start);
1944	2947
	2948	+ /*
	2949	+ * CLK_ALWAYS_ON should be placed after all registers write done,
	2950	+ * because this situation will enable XFER bit which will make
	2951	+ * some registers(depend on XFER) write failed.
	2952	+ */
	2953	+ if (i2s_tdm->quirks & QUIRK_ALWAYS_ON) {
	2954	+ ret = rockchip_i2s_tdm_keep_clk_always_on(i2s_tdm);
	2955	+ if (ret)
	2956	+ return ret;
	2957	+ }
	2958	+
	2959	+ /*
	2960	+ * MUST: after pm_runtime_enable step, any register R/W
	2961	+ * should be wrapped with pm_runtime_get_sync/put.
	2962	+ *
	2963	+ * Another approach is to enable the regcache true to
	2964	+ * avoid access HW registers.
	2965	+ *
	2966	+ * Alternatively, performing the registers R/W before
	2967	+ * pm_runtime_enable is also a good option.
	2968	+ */
	2969	+ pm_runtime_enable(&pdev->dev);
	2970	+ if (!pm_runtime_enabled(&pdev->dev)) {
	2971	+ ret = i2s_tdm_runtime_resume(&pdev->dev);
	2972	+ if (ret)
	2973	+ goto err_pm_disable;
	2974	+ }
	2975	+
	2976	+ ret = rockchip_i2s_tdm_register_platform(&pdev->dev);
	2977	+ if (ret)
	2978	+ goto err_suspend;
	2979	+
1945	2980	ret = devm_snd_soc_register_component(&pdev->dev,
1946	2981	&rockchip_i2s_tdm_component,
1947	2982	soc_dai, 1);
1948		-
1949	2983	if (ret) {
1950	2984	dev_err(&pdev->dev, "Could not register DAI\n");
1951	2985	goto err_suspend;
1952		- }
1953		-
1954		- if (of_property_read_bool(node, "rockchip,no-dmaengine"))
1955		- return ret;
1956		- ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1957		- if (ret) {
1958		- dev_err(&pdev->dev, "Could not register PCM\n");
1959		- return ret;
1960	2986	}
1961	2987
1962	2988	return 0;
..	..	@@ -1978,14 +3004,21 @@
1978	3004	if (!pm_runtime_status_suspended(&pdev->dev))
1979	3005	i2s_tdm_runtime_suspend(&pdev->dev);
1980	3006
1981		- if (!IS_ERR(i2s_tdm->mclk_tx))
1982		- clk_prepare_enable(i2s_tdm->mclk_tx);
1983		- if (!IS_ERR(i2s_tdm->mclk_rx))
1984		- clk_prepare_enable(i2s_tdm->mclk_rx);
1985		- if (!IS_ERR(i2s_tdm->hclk))
1986		- clk_disable_unprepare(i2s_tdm->hclk);
	3007	+ clk_disable_unprepare(i2s_tdm->mclk_tx);
	3008	+ clk_disable_unprepare(i2s_tdm->mclk_rx);
	3009	+ clk_disable_unprepare(i2s_tdm->hclk);
1987	3010
1988	3011	return 0;
	3012	+}
	3013	+
	3014	+static void rockchip_i2s_tdm_platform_shutdown(struct platform_device *pdev)
	3015	+{
	3016	+ struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(&pdev->dev);
	3017	+
	3018	+ pm_runtime_get_sync(i2s_tdm->dev);
	3019	+ rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
	3020	+ rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_CAPTURE);
	3021	+ pm_runtime_put(i2s_tdm->dev);
1989	3022	}
1990	3023
1991	3024	#ifdef CONFIG_PM_SLEEP
..	..	@@ -2023,6 +3056,7 @@
2023	3056	static struct platform_driver rockchip_i2s_tdm_driver = {
2024	3057	.probe = rockchip_i2s_tdm_probe,
2025	3058	.remove = rockchip_i2s_tdm_remove,
	3059	+ .shutdown = rockchip_i2s_tdm_platform_shutdown,
2026	3060	.driver = {
2027	3061	.name = DRV_NAME,
2028	3062	.of_match_table = of_match_ptr(rockchip_i2s_tdm_match),