debug lk

hc

2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077

 kernel/sound/soc/rockchip/rockchip_i2s.h
..
..
@@ -18,8 +18,9 @@
18
18
 #define I2S_TXCR_RCNT_SHIFT	17
19
19
 #define I2S_TXCR_RCNT_MASK	(0x3f << I2S_TXCR_RCNT_SHIFT)
20
20
 #define I2S_TXCR_CSR_SHIFT	15
21
-#define I2S_TXCR_CSR(x)		(x << I2S_TXCR_CSR_SHIFT)
22
21
 #define I2S_TXCR_CSR_MASK	(3 << I2S_TXCR_CSR_SHIFT)
22
+#define I2S_TXCR_CSR(x)		(x << I2S_TXCR_CSR_SHIFT)
23
+#define I2S_TXCR_CSR_V(v)	((((v) & I2S_TXCR_CSR_MASK) >> 15) + 1)
23
24
 #define I2S_TXCR_HWT		BIT(14)
24
25
 #define I2S_TXCR_SJM_SHIFT	12
25
26
 #define I2S_TXCR_SJM_R		(0 << I2S_TXCR_SJM_SHIFT)
..
..
@@ -48,8 +49,9 @@
48
49
  * receive operation control register
49
50
 */
50
51
 #define I2S_RXCR_CSR_SHIFT	15
51
-#define I2S_RXCR_CSR(x)		(x << I2S_RXCR_CSR_SHIFT)
52
52
 #define I2S_RXCR_CSR_MASK	(3 << I2S_RXCR_CSR_SHIFT)
53
+#define I2S_RXCR_CSR(x)		(x << I2S_RXCR_CSR_SHIFT)
54
+#define I2S_RXCR_CSR_V(v)	((((v) & I2S_RXCR_CSR_MASK) >> 15) + 1)
53
55
 #define I2S_RXCR_HWT		BIT(14)
54
56
 #define I2S_RXCR_SJM_SHIFT	12
55
57
 #define I2S_RXCR_SJM_R		(0 << I2S_RXCR_SJM_SHIFT)
..
..
@@ -132,14 +134,16 @@
132
134
 #define I2S_DMACR_RDE_DISABLE	(0 << I2S_DMACR_RDE_SHIFT)
133
135
 #define I2S_DMACR_RDE_ENABLE	(1 << I2S_DMACR_RDE_SHIFT)
134
136
 #define I2S_DMACR_RDL_SHIFT	16
135
-#define I2S_DMACR_RDL(x)	((x - 1) << I2S_DMACR_RDL_SHIFT)
136
137
 #define I2S_DMACR_RDL_MASK	(0x1f << I2S_DMACR_RDL_SHIFT)
138
+#define I2S_DMACR_RDL(x)	((x - 1) << I2S_DMACR_RDL_SHIFT)
139
+#define I2S_DMACR_RDL_V(v)	((((v) & I2S_DMACR_RDL_MASK) >> 16) + 1)
137
140
 #define I2S_DMACR_TDE_SHIFT	8
138
141
 #define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
139
142
 #define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
140
143
 #define I2S_DMACR_TDL_SHIFT	0
141
-#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
142
144
 #define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
145
+#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
146
+#define I2S_DMACR_TDL_V(v)	(((v) & I2S_DMACR_TDL_MASK) >> 0)
143
147
 
144
148
 /*
145
149
  * INTCR
..
..
@@ -229,7 +233,7 @@
229
233
 #define I2S_TXCR	(0x0000)
230
234
 #define I2S_RXCR	(0x0004)
231
235
 #define I2S_CKR		(0x0008)
232
-#define I2S_FIFOLR	(0x000c)
236
+#define I2S_TXFIFOLR	(0x000c)
233
237
 #define I2S_DMACR	(0x0010)
234
238
 #define I2S_INTCR	(0x0014)
235
239
 #define I2S_INTSR	(0x0018)
..
..
@@ -237,6 +241,7 @@
237
241
 #define I2S_CLR		(0x0020)
238
242
 #define I2S_TXDR	(0x0024)
239
243
 #define I2S_RXDR	(0x0028)
244
+#define I2S_RXFIFOLR	(0x002c)
240
245
 
241
246
 /* io direction cfg register */
242
247
 #define I2S_IO_DIRECTION_MASK	(7)
..
..
@@ -245,4 +250,11 @@
245
250
 #define I2S_IO_4CH_OUT_6CH_IN	(6)
246
251
 #define I2S_IO_2CH_OUT_8CH_IN	(7)
247
252
 
253
+/* XFL4 is compatible for old version */
254
+#define I2S_FIFOLR_XFL4(v)	(((v) & GENMASK(29, 24)) >> 24)
255
+#define I2S_FIFOLR_XFL3(v)	(((v) & GENMASK(23, 18)) >> 18)
256
+#define I2S_FIFOLR_XFL2(v)	(((v) & GENMASK(17, 12)) >> 12)
257
+#define I2S_FIFOLR_XFL1(v)	(((v) & GENMASK(11, 6)) >> 6)
258
+#define I2S_FIFOLR_XFL0(v)	(((v) & GENMASK(5, 0)) >> 0)
259
+
248
260
 #endif /* _ROCKCHIP_IIS_H */