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2024-02-20 e636c8d336489bf3eed5878299e6cc045bbad077 
 kernel/include/dt-bindings/iio/qcom,spmi-vadc.h
....@@ -1,14 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
12 /*
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- * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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+ * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
124  */
135 
146 #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
....@@ -116,4 +108,193 @@
116108 #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID	0xf9
117109 #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM	0xfc
118110 
111
+/* ADC channels for SPMI PMIC5 */
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+
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+#define ADC5_REF_GND				0x00
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+#define ADC5_1P25VREF				0x01
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+#define ADC5_VREF_VADC				0x02
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+#define ADC5_VREF_VADC5_DIV_3			0x82
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+#define ADC5_VPH_PWR				0x83
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+#define ADC5_VBAT_SNS				0x84
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+#define ADC5_VCOIN				0x85
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+#define ADC5_DIE_TEMP				0x06
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+#define ADC5_USB_IN_I				0x07
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+#define ADC5_USB_IN_V_16			0x08
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+#define ADC5_CHG_TEMP				0x09
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+#define ADC5_BAT_THERM				0x0a
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+#define ADC5_BAT_ID				0x0b
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+#define ADC5_XO_THERM				0x0c
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+#define ADC5_AMUX_THM1				0x0d
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+#define ADC5_AMUX_THM2				0x0e
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+#define ADC5_AMUX_THM3				0x0f
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+#define ADC5_AMUX_THM4				0x10
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+#define ADC5_AMUX_THM5				0x11
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+#define ADC5_GPIO1				0x12
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+#define ADC5_GPIO2				0x13
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+#define ADC5_GPIO3				0x14
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+#define ADC5_GPIO4				0x15
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+#define ADC5_GPIO5				0x16
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+#define ADC5_GPIO6				0x17
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+#define ADC5_GPIO7				0x18
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+#define ADC5_SBUx				0x99
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+#define ADC5_MID_CHG_DIV6			0x1e
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+#define ADC5_OFF				0xff
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+
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+/* 30k pull-up1 */
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+#define ADC5_BAT_THERM_30K_PU			0x2a
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+#define ADC5_BAT_ID_30K_PU			0x2b
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+#define ADC5_XO_THERM_30K_PU			0x2c
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+#define ADC5_AMUX_THM1_30K_PU			0x2d
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+#define ADC5_AMUX_THM2_30K_PU			0x2e
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+#define ADC5_AMUX_THM3_30K_PU			0x2f
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+#define ADC5_AMUX_THM4_30K_PU			0x30
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+#define ADC5_AMUX_THM5_30K_PU			0x31
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+#define ADC5_GPIO1_30K_PU			0x32
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+#define ADC5_GPIO2_30K_PU			0x33
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+#define ADC5_GPIO3_30K_PU			0x34
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+#define ADC5_GPIO4_30K_PU			0x35
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+#define ADC5_GPIO5_30K_PU			0x36
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+#define ADC5_GPIO6_30K_PU			0x37
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+#define ADC5_GPIO7_30K_PU			0x38
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+#define ADC5_SBUx_30K_PU			0x39
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+
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+/* 100k pull-up2 */
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+#define ADC5_BAT_THERM_100K_PU			0x4a
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+#define ADC5_BAT_ID_100K_PU			0x4b
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+#define ADC5_XO_THERM_100K_PU			0x4c
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+#define ADC5_AMUX_THM1_100K_PU			0x4d
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+#define ADC5_AMUX_THM2_100K_PU			0x4e
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+#define ADC5_AMUX_THM3_100K_PU			0x4f
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+#define ADC5_AMUX_THM4_100K_PU			0x50
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+#define ADC5_AMUX_THM5_100K_PU			0x51
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+#define ADC5_GPIO1_100K_PU			0x52
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+#define ADC5_GPIO2_100K_PU			0x53
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+#define ADC5_GPIO3_100K_PU			0x54
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+#define ADC5_GPIO4_100K_PU			0x55
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+#define ADC5_GPIO5_100K_PU			0x56
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+#define ADC5_GPIO6_100K_PU			0x57
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+#define ADC5_GPIO7_100K_PU			0x58
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+#define ADC5_SBUx_100K_PU			0x59
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+
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+/* 400k pull-up3 */
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+#define ADC5_BAT_THERM_400K_PU			0x6a
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+#define ADC5_BAT_ID_400K_PU			0x6b
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+#define ADC5_XO_THERM_400K_PU			0x6c
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+#define ADC5_AMUX_THM1_400K_PU			0x6d
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+#define ADC5_AMUX_THM2_400K_PU			0x6e
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+#define ADC5_AMUX_THM3_400K_PU			0x6f
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+#define ADC5_AMUX_THM4_400K_PU			0x70
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+#define ADC5_AMUX_THM5_400K_PU			0x71
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+#define ADC5_GPIO1_400K_PU			0x72
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+#define ADC5_GPIO2_400K_PU			0x73
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+#define ADC5_GPIO3_400K_PU			0x74
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+#define ADC5_GPIO4_400K_PU			0x75
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+#define ADC5_GPIO5_400K_PU			0x76
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+#define ADC5_GPIO6_400K_PU			0x77
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+#define ADC5_GPIO7_400K_PU			0x78
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+#define ADC5_SBUx_400K_PU			0x79
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+
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+/* 1/3 Divider */
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+#define ADC5_GPIO1_DIV3				0x92
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+#define ADC5_GPIO2_DIV3				0x93
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+#define ADC5_GPIO3_DIV3				0x94
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+#define ADC5_GPIO4_DIV3				0x95
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+#define ADC5_GPIO5_DIV3				0x96
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+#define ADC5_GPIO6_DIV3				0x97
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+#define ADC5_GPIO7_DIV3				0x98
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+#define ADC5_SBUx_DIV3				0x99
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+
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+/* Current and combined current/voltage channels */
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+#define ADC5_INT_EXT_ISENSE			0xa1
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+#define ADC5_PARALLEL_ISENSE			0xa5
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+#define ADC5_CUR_REPLICA_VDS			0xa7
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+#define ADC5_CUR_SENS_BATFET_VDS_OFFSET		0xa9
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+#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET	0xab
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+#define ADC5_EXT_SENS_OFFSET			0xad
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+
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+#define ADC5_INT_EXT_ISENSE_VBAT_VDATA		0xb0
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+#define ADC5_INT_EXT_ISENSE_VBAT_IDATA		0xb1
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+#define ADC5_EXT_ISENSE_VBAT_VDATA		0xb2
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+#define ADC5_EXT_ISENSE_VBAT_IDATA		0xb3
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+#define ADC5_PARALLEL_ISENSE_VBAT_VDATA		0xb4
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+#define ADC5_PARALLEL_ISENSE_VBAT_IDATA		0xb5
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+
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+#define ADC5_MAX_CHANNEL			0xc0
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+
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+/* ADC channels for ADC for PMIC7 */
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+
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+#define ADC7_REF_GND				0x00
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+#define ADC7_1P25VREF				0x01
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+#define ADC7_VREF_VADC				0x02
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+#define ADC7_DIE_TEMP				0x03
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+
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+#define ADC7_AMUX_THM1				0x04
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+#define ADC7_AMUX_THM2				0x05
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+#define ADC7_AMUX_THM3				0x06
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+#define ADC7_AMUX_THM4				0x07
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+#define ADC7_AMUX_THM5				0x08
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+#define ADC7_AMUX_THM6				0x09
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+#define ADC7_GPIO1				0x0a
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+#define ADC7_GPIO2				0x0b
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+#define ADC7_GPIO3				0x0c
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+#define ADC7_GPIO4				0x0d
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+
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+#define ADC7_CHG_TEMP				0x10
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+#define ADC7_USB_IN_V_16			0x11
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+#define ADC7_VDC_16				0x12
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+#define ADC7_CC1_ID				0x13
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+#define ADC7_VREF_BAT_THERM			0x15
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+#define ADC7_IIN_FB				0x17
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+
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+/* 30k pull-up1 */
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+#define ADC7_AMUX_THM1_30K_PU			0x24
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+#define ADC7_AMUX_THM2_30K_PU			0x25
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+#define ADC7_AMUX_THM3_30K_PU			0x26
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+#define ADC7_AMUX_THM4_30K_PU			0x27
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+#define ADC7_AMUX_THM5_30K_PU			0x28
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+#define ADC7_AMUX_THM6_30K_PU			0x29
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+#define ADC7_GPIO1_30K_PU			0x2a
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+#define ADC7_GPIO2_30K_PU			0x2b
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+#define ADC7_GPIO3_30K_PU			0x2c
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+#define ADC7_GPIO4_30K_PU			0x2d
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+#define ADC7_CC1_ID_30K_PU			0x33
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+
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+/* 100k pull-up2 */
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+#define ADC7_AMUX_THM1_100K_PU			0x44
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+#define ADC7_AMUX_THM2_100K_PU			0x45
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+#define ADC7_AMUX_THM3_100K_PU			0x46
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+#define ADC7_AMUX_THM4_100K_PU			0x47
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+#define ADC7_AMUX_THM5_100K_PU			0x48
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+#define ADC7_AMUX_THM6_100K_PU			0x49
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+#define ADC7_GPIO1_100K_PU			0x4a
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+#define ADC7_GPIO2_100K_PU			0x4b
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+#define ADC7_GPIO3_100K_PU			0x4c
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+#define ADC7_GPIO4_100K_PU			0x4d
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+#define ADC7_CC1_ID_100K_PU			0x53
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+
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+/* 400k pull-up3 */
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+#define ADC7_AMUX_THM1_400K_PU			0x64
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+#define ADC7_AMUX_THM2_400K_PU			0x65
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+#define ADC7_AMUX_THM3_400K_PU			0x66
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+#define ADC7_AMUX_THM4_400K_PU			0x67
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+#define ADC7_AMUX_THM5_400K_PU			0x68
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+#define ADC7_AMUX_THM6_400K_PU			0x69
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+#define ADC7_GPIO1_400K_PU			0x6a
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+#define ADC7_GPIO2_400K_PU			0x6b
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+#define ADC7_GPIO3_400K_PU			0x6c
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+#define ADC7_GPIO4_400K_PU			0x6d
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+#define ADC7_CC1_ID_400K_PU			0x73
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+
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+/* 1/3 Divider */
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+#define ADC7_GPIO1_DIV3				0x8a
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+#define ADC7_GPIO2_DIV3				0x8b
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+#define ADC7_GPIO3_DIV3				0x8c
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+#define ADC7_GPIO4_DIV3				0x8d
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+
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+#define ADC7_VPH_PWR				0x8e
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+#define ADC7_VBAT_SNS				0x8f
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+
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+#define ADC7_SBUx				0x94
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+#define ADC7_VBAT_2S_MID			0x96
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+
119300 #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */